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Efficient Floating-Point Implementation of the Probit Function on FPGAs

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Abstract

Non-uniform random number generators are key components in Monte Carlo simulations. The inverse cumulative distribution function (ICDF) technique provides a viable solution for generating random variables from various distributions. Thus, the ICDF of the standard normal distribution, or probit function for short, is of particular interest. The goal of this article is to revisit and improve a floating-point (FP) implementation of probit, from the perspective of modern hardware resources available on FPGAs. Beside reexamining the classical Wichura’s algorithm, we propose: (1) a single-precision implementation using the embedded FP DSP Blocks available in recent FPGA families; (2) generic custom-precision architectures that scale up to double-precision. These present a user-selectable trade-off between tail accuracy and resource utilization. Our proposed cores outperform existing single-precision FPGA implementations in area, latency and accuracy, and also set benchmarks for new custom and double-precision FP implementations.

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Notes

  1. stat.ethz.ch/R-manual/R-devel/library/base/html/Random.html

  2. These correspond to formats with the same dynamic range as the binary64, but less precision, which can be useful for some applications. The fraction widths are chosen based on existing FP formats in the DSP Builder Advanced Blockset [3, Section 10.2].

  3. Available at http://homepages.laas.fr/mmjoldes/probit

  4. The absolute accuracy test in line 2 can be made relative by dividing with w0, provided that w0≠ 0

  5. The multiplication by 2 in the previous change of variable is simply related to the fact that the probit function is the inverse erf function of argument 2x − 1 (see Eq. 2), so the approximations and segmentations will be directly related to those of the inverse error function which is symmetric around 0.

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Correspondence to Mioara Joldes.

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Joldes, M., Pasca, B. Efficient Floating-Point Implementation of the Probit Function on FPGAs. J Sign Process Syst 93, 1387–1403 (2021). https://doi.org/10.1007/s11265-021-01692-w

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