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Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation

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Abstract

Low-latency and energy-efficient multi-Gbps LDPC decoding requires fast-converging iterative schedules. Hardware decoder architectures based on such schedules can achieve high throughput at low clock speeds, resulting in reduced power consumption and relaxed timing closure requirements for physical VLSI design. In this work, a fast column message-passing (FCMP) schedule for decoding LDPC codes is presented and investigated. FCMP converges in half the number of iterations compared to existing serial decoding schedules, has a significantly lower computational complexity than residual-belief-propagation (RBP)-based schedules, and consumes less power compared to state-of-the-art schedules. An FCMP decoder architecture supporting IEEE 802.11ad (WiGig) LDPC codes is presented. The decoder is fully pipelined to decode two frames with no idle cycles. The architecture is synthesized using the TSMC 40 nm and 65 nm CMOS technology nodes, and operates at a clock-frequency of 200 MHz. The decoder achieves a throughput of 8.4 Gbps, and it consumes 72 mW of power when synthesized using the 40 nm technology node. This results in an energy efficiency of 8.6 pJ/bit, which is the best-reported energy-efficiency in the literature for a WiGig LDPC decoder.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, American University of Beirut, Beirut, Lebanon

    Saleh Usman & Mohammad M. Mansour

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  1. Saleh Usman
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  2. Mohammad M. Mansour
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Correspondence to Saleh Usman.

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Usman, S., Mansour, M.M. Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation. J Sign Process Syst 93, 1271–1286 (2021). https://doi.org/10.1007/s11265-021-01680-0

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  • DOI: https://doi.org/10.1007/s11265-021-01680-0

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