Abstract
A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based on switching activity analysis of each logic sub-blocks is presented to explore the optimal solution. The parabolic equations with proper selection of coefficients and pipeline structure are utilized to enhance SFDR. A ROM-less DDFS using the proposed design approach is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.
Similar content being viewed by others
References
Sun, Y., Yu, X., Rhee, W., Wang, D., Wang, Z. (2010). A fast settling dual-path fractional-N PLL with hybrid-mode dynamic bandwidth control. IEEE Microwave and Wireless Components Letters, 20(8), 462–464.
Tierney, J., Rader, C., Gold, B. (1971). A digital frequency synthesizer. IEEE Transactions on Audio and Electroacoustics, 19(1), 48–57.
Pontikakis, B., Bui, H.-T., Boyer, F.-R., Savaria, Y. (2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation. In: IEEE MidWest Symposium on Circuits and Systems 2007 (MWSCAS ’07) (pp. 1118–1121).
Sotiriadis, P. (2009). Timing and spectral properties of the Flying Adder frequency synthesizers. IEEE International Frequency Control Symposium, 2009, 788–792.
Wang, C.-C., Hsu, C.-H., Lee, C.-C., Huang, J.-M. (2010). A ROM-less DDFS based on a parabolic polynomial interpolation method with an offset. Journal of Signal Processing Systems, 61, 1–9.
Cali, J., Geng, X., Zhao, F., Pukish, M., Dai, F., Aklian, A. (2013). A 650 MHz DDFS for stretch processing radar in 130nm biCMOS process. In Proc. European Microwave Integrated Circuit Conference (EMICC) (pp. 33–36).
Padash, M., Toofan, S., Yargholi, M. (2014). A 9-bit, 1-giga samples per second sine and cosine direct digital frequency synthesizer. In Proc. Iranian Conf. on Electrical Engineering (ICEE) (pp 438–442).
de Carvalho, P.R.B., Palacio, J.A.A., Van Noije, W. (2016). Area optimized CORDIC-based numerically controlled oscillator for electrical bio-impedance spectroscopy. In Proc. IEEE Int. Freq. Control Symposium (IFCS) (pp. 1–6).
Hsu, C.-H., Chen, Y.-C., Wang, C.-C. (2011). ROM-less DDFS using non-equal division parabolic polynomial interpolation method. In Proc. Int. Symp. on Integrated Circuits (ISIC) (pp. 59–62).
Geng, X., Dai, F.F., Irwin, J.D., Jaeger, R.C. (2010). An 11-Bit 8.6 GHz direct digital synthesizer MMIC with 10-Bit segmented sine-weighted DAC. IEEE Journal of Solid-State Circuits (JSSC), 45(2), 300–313.
Wang, C.-C., Huang, J.-M., Tseng, Y.-L., Lin, W.-J., Hu, R. (2006). Phase-adjustable pipelining ROM-less direct digital frequency synthesizer with a 41.66-MHz output frequency. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(10), 1143–1147.
Lopelli, E., van der Tang, J.D., Roermund, A.H.M. (2009). Minimum power-consumption estimation in ROM-based DDFS for frequency-hopping ultralow-power transmitters. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(1), 256–267.
Tsai, J.-Y. (2007). Low power techniques for digital IC design. CICeNEWS, 86, 1–22.
Wang, W., Xu, Y.-Y., Wang, C.-C. (2017). Dynamic power estimation for ROM-less DDFS designs using switching activity analysis. In 2017 The 14th Inter. SoC Design Conf. (pp. 280–281).
Alonso, A.M., Yuan, X., Miyahara, M., Matsuzawa, A. (2017). A 2 GS/s 118 mW digital-mapping direct digital frequency synthesizer in 65nm CMOS. In 12th European Microwave Integrated Circuits Conference (ISSCC 2003) (pp. 228–231).
Suryavanshi, R., Sridevi, S., Amrutur, B. (2017). A comparative study of direct digital frequency synthesizer architectures in 180 nm CMOS. In International Conference on Microelectronic Devices, Circuits and Systems. (ICMDCS 2017) (pp. 1–5).
Acknowledgment
This investigation is partially supported by Ministry of Science and Technology, Taiwan, under grant MOST 107-2218-E-110-004- and 107-2221-E-006-232-. The authors would also like to express their deepest gratefulness to Chip Implementation Center of National Applied Research Laboratories, Taiwan, for their thoughtful chip fabrication service and EDA tool support.
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Wang, CC., Sulistiyanto, N., Shih, HY. et al. Power-effective ROM-less DDFS Design Approach with High SFDR Performance. J Sign Process Syst 92, 213–224 (2020). https://doi.org/10.1007/s11265-019-01460-x
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-019-01460-x