Low power pipeline-parallel phase accumulator

Abstract

In this brief, a low power pipeline-parallel phase accumulator (PPA) with 32-bit frequency resolution and 10-bit phase resolution is proposed for direct digital frequency synthesizer (DDFS) applications. The proposed PPA is derived using the conventional pipeline and parallel phase accumulator (PA) architectures. To assess the performance of the proposed PPA, it is compared against the existing PAs in terms of design metrics (DMs) such as power, area, and a maximum frequency of operation. For a fair comparison, the PPA and existing PAs have been described using Verilog register-transfer-level (RTL) codes and synthesized under common constraints, using TSMC typical 180 nm standard cell library. The constraints used are the input delay = 250 ns, output delay = 250 ns, supply voltage $V_{dd}$ = 1.8 V, and clock frequency ($f_{clk}$) = 100 MHz. Cadence’s RC tool-based synthesis results show that the proposed PPA has a total power $P_{T}$ = 791.35 nW, area = 9307.26 $\mu m^{2}$, and $f_{max}$=890 MHz. The proposed PPA saves 16.83% of total power and 3.31% of total area against the reported pipeline-parallel PA.