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A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram

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Abstract

Phase change RAM (PRAM) is a promising memory technology because of its fast read access time, very low standby power and high storage density. Multi-level Cell (MLC) PRAM, which has been introduced to further improve the storage density, comes at a price of lower reliability. This paper focuses on a cost-effective solution for improving the reliability of MLC-PRAM. As a first step, we study in detail the causes of hard and soft errors and develop error models to capture these effects. Next we propose a multi-tiered approach that spans architecture, circuit and system levels to increase the reliability. At the architecture level, we use a combination of Gray code encoding and 2-bit interleaving to partition the errors so that a lower strength error control coding (ECC) scheme can be used for half of the bits. We use subblock flipping and threshold resistance tuning to reduce the number of errors in the remaining bits. For even higher reliability, we use a simple BCH based ECC on top of these techniques. We show that the proposed multi-tiered approach enables us to use ECC with 2-error correction capability (t = 2) instead of one with t = 8 to achieve a block failure rate (BFR) of 10−8. We propose to use a non-iterative algorithm to implement the BCH t = 2 decoder because of its small latency. We evaluate the latency and energy overhead of the proposed scheme using CACTI and the IPC performance using GEM5. We show that for SPEC CINT 2006 and DaCapo benchmarks, the proposed system can achieve BFR = 10−8 with 2.2 % IPC reduction and 7 % additional energy compared to a memory without any error correction capability.

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Notes

  1. 1 The extensions include (i) updated PRAM device model in Section 2.1, (ii) justification of use of single iteration of subblock flipping in Section 4.2, (iii) use of non-iterative BCH decoder to reduce latency in Section 6.2 and (iv) evaluation of system-level latency and energy using CACTI followed by IPC evaluation using GEM5 in Section 7.

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Acknowledgments

This work was supported in part by a grant from NSF CSR 0910699.

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Correspondence to Chengen Yang.

Appendix A. Non-Iterative Decoding Algorithm of BCH(t = 2)

Appendix A. Non-Iterative Decoding Algorithm of BCH(t = 2)

Binary BCH code (n, k) in GF(2m) has code length n = 2m − 1, k information bits and nk parity bits, m ≥ 3. The decoding of BCH code consists of three steps: syndrome calculation, error locator polynomial generation and finding the error location. Let α be the primitive element of GF(2m). If α i, α j …. α k are the roots of the error locator polynomial, then the corresponding error locations are ni, nj, …. nk.

Let \( \overset{\rightharpoonup }{r}=\left({r}_0,{r}_1,\dots, {r}_{n-1}\right) \) be the received vector, then in the syndrome calculation, the decoder calculates the syndrome vector, \( \overset{\rightharpoonup }{S}=\overset{\rightharpoonup }{r}\cdotp {H}^T \), where H is the parity check matrix. When t = 2, S = (s 1, s 2, s 3, s 4) and decoder only uses s 1 and s 3 to determine the error scenario [26].

In the error locator polynomial generation, if there is no error, \( \overset{\rightharpoonup }{S}=0 \).

If there is one error in \( \overset{\rightharpoonup }{r} \), then \( \overset{\rightharpoonup }{S}\ne 0 \) and  s 3 = s 31 . The error locator polynomial σ(x) is

$$ \sigma (x)=1+{s}_1x. $$
(8)

If there are two errors in \( \overset{\rightharpoonup }{r} \), then \( \overset{\rightharpoonup }{S}\ne 0 \) and  s 3 ≠ s 31 and the error locator polynomial σ(x) is

$$ \sigma (x)=1+{s}_1x+\left({s}_1^2+{s}_3/{s}_1\right){x}^2. $$
(9)

In (8), if s 1 = α i, then the root is α j, j = ni, and the error is in the i th bit in \( \overset{\rightharpoonup }{r} \).

Polynomial (9) can be further presented as

$$ K+y+{y}^2=0 $$
(10)

where K = 1 + S 3/S 31 , and y = x · (s 31  + s 3)/s 21 [27, 28]. When m is odd, the roots y 1 and y 2 can be directly derived by \( {y}_1={\displaystyle \sum}_{a\in A}{K}^{2^a}={\displaystyle \sum}_{b\in B}{K}^{2^b} \), where A = {1, 3, 5, …, m − 2} and B = {0, 2, 4, …, m − 1} and y 2 = 1 + y 1. We use this method since m = 9 in the BCH decoder in Scheme 2. Note that y 1 and y 2 are multiplied by (s 21 /(s 31  + s 3)), to get the two roots of (9).

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Yang, C., Emre, Y., Xu, Z. et al. A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram. J Sign Process Syst 76, 133–147 (2014). https://doi.org/10.1007/s11265-013-0856-x

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