Over the past 10 years, broadband communications have become the major focus for industry for offering rich multimedia services. As new video-rich and bandwidth-hungry services are developed, the challenge to deliver the next generation broadband services is becoming more profound. In addition, energy-efficient circuits and systems for broadband communications require systematic optimization at all levels of design abstraction ranging from process technology and logic design to architectures and algorithms.

However, the straightforward VLSI implementation of broadband communication systems is associated with considerable silicon area and high power consumption. These issues pose unprecedented challenges for the design and implementation of highly practical and reliable circuits and systems for broadband communications. The signal processing research for broadband communications needs to address a plurality of issues ranging from the development of high-speed signal processing techniques to the implementation of compact transceiver architectures with low power consumption. In addition, the signal processing technology for broadband communications requires more studies not only from the perspective of wireless systems, but also in the area of high-speed optical and satellite communication systems.

This special issue intends to present the latest state-of-the-art research results in the area of signal processing circuits and systems for broadband communications. The topics included range from algorithm development to implementation and system design. All papers were thoroughly reviewed according to the standard peer review process of the Journal of Signal Processing Systems.

The first two papers provide interesting insights into Reed-Solomon (RS) Decoders. “Modified Low-Complexity Chase Soft-Decision Decoder of Reed-Solomon Codes,” by Xinmiao Zhang, et al. exploits the low-complexity Chase (LCC) algorithm, which can achieve better performance-complexity tradeoff compared to other decoding algorithms of RS codes. Through adding common erasures to the test vectors, a modified LCC (MLCC) decoding is proposed to combat inter-symbol interference. It leads to significant reductions on both silicon area and average decoding latency without incurring any performance loss. The second paper, “Three-Parallel Reed-Solomon Decoder using S-DCME for High-Speed Communications,” by Jae Do Lee et al. proposes a high-speed and area-efficient three-parallel RS decoder. The high throughput and efficiency are achieved through computing the inner signals in parallel and solving the key equation using the simplified degree computationless modified Euclid (S-DCME) algorithm.

The next two papers focus on the design of a Turbo decoder for multi-standards and a BCH decoder for 100Gb/s optical communications. “Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support,” by Rizwan Asghar et al. offers a unified architecture supporting radix-4 turbo decoders for multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The support of multi-standards is mainly achieved through modifying the schemes for Turbo code interleavers used in different standards. The proposed architecture achieves smaller silicon area, lower power consumption and higher throughput, while maintaining reconfigurablity on-the-fly. The paper “A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100Gb/s Optical Communications,” by Kihoon Lee et al. presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability.

The fifth paper presents a time-division multiplexing (TDM) switch integrated circuit (IC). It is “An 8 × 8 20Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking” by Ching-Te Chiu, et al. In this paper, the authors fold the two-stage switch to reduce 50% hardware complexity, and then implement a prototype switch fabric IC, including a digital 8 × 8 switch core, eight SERDES ports with I/O interfaces and a phase-lock loop, in 0.18 μm CMOS technology. Measurements show that the 8 × 8 switch fabric IC can achieve 20Gbps switching rate and consumes only about 690 mW power.

The last paper, “On the Achievable Rate for Wideband Channels with Estimated CSI,” by Jinho Choi et al. attempts to find the achievable rate for frequency-selective fading channels when the channels are to be estimated. Since some portion of the radio resources is consumed to estimate the channel state information (CSI), it should be taken into account in finding the achievable rate. This work is useful in designing flexible radio systems such as software defined radio.

We would like to thank the authors for their work in submitting and revising the manuscripts. It has been gratifying to learn more about the advances of signal processing circuits and systems for broadband communications. We also wish to express our deepest gratitude for the efforts of the reviewers. This special issue is only possible with their expert help.

Myung Hoon Sunwoo

Guest Editor