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VHDL Design for Real Time Motion Estimation Video Applications

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Abstract

The VHDL design code and its implementation using 0.25 μm technology have been demonstrated for the real time video applications. The processing time of a frame running at 400 MHz was estimated to be 8.1 ms for QCIF and CIF Sequences, which accommodates more than 120 frames per second, and this warrant real time video codec. The design was validated and simulated using ModelSim from Mentor Graphics tools, and then verified using both the VHDL testbench and the Matlab® Image processing toolbox. Various alternate search algorithms have been proposed and simulated using Matlab for their real time processing. Skipping “every other column” (SC), and skipping “every other row and column” (SRC) algorithm, “optimal local neighborhood search” (OLNS), and limited-optimal neighborhood search (L-OLNS) have been demonstrated. The microprocessor as a controller is based on RISC processor and it uses pipelining to gain clocking efficiency.

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References

  1. Hsieh, C. H., & Lin, T. P. (1992). VLSI architecture for block-matching motion estimation algorithm. IEEE Transactions on Circuits and Systems for Video Technology, 2(2), 169–175 (June).

    Article  Google Scholar 

  2. Yang, K. M., Sun, M. T., & Wu, L. (1989). A family of VLSI designs for the motion compensation block-matching algorithm. IEEE Transactions on Circuits and Systems, 36(10), 1317–1325 (October).

    Article  Google Scholar 

  3. Komarek, T., & Pirsch, P. (1989). Array architectures for block matching algorithms. IEEE Transactions on Circuits and Systems, 36(10), 1301–1308 (October).

    Article  Google Scholar 

  4. Vos, L. D., & Stegherr, M. (1989). Parameterizable VLSI architectures for the full-search block-matching algorithm. IEEE Transactions on Circuits and Systems, 36(10), 1309–1316 (October).

    Article  Google Scholar 

  5. Bhaskaran, V., & Konstantinides, K. (1997). Image and video compression standards. Norwell, MA: Kluwer.

    Google Scholar 

  6. Seo, Y. S., & You, J. H. A VLSI design of hierarchical search motion estimation processor chip. School of Electrical and Computer Engineering, Hongik University, Seoul, Korea.

  7. Dioago, Z., Luigi, C., &Sergio, B., & Altamiro, S. (2001). An architecture for MPEG motion estimation. VII Workshop Iberchip IWS’2001, Montevideo, 1. pp. 90–95.

  8. Baek, Y., Oh, H. S., & Lee, H. K. (1996). An efficient block-matching criterion for motion estimation and its VLSI implementation. IEEE Transactions on Consumer Electronics, 2(4), 885–889 (November).

    Article  Google Scholar 

  9. Chang, S., Hwang, J. H., & Jen, C. W. (1995). Scalable array architecture design for full-search block-matching. IEEE Transactions on Circuits and Systems for Video Technology, 5(4), 332–343 (August).

    Article  Google Scholar 

  10. Yeo, H., & Hu, Y. H. (1995). A novel modular systolic array architecture for full search block-matching motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 5(5), 407–415 (October).

    Article  Google Scholar 

  11. Sanz, C., Garrido, M. J., & Meneses, J. M. (1996). VLSI architecture for motion estimation using the block-matching algorithm. Proceedings of European Design and Test Conference, ED & TC ’96, Paris, France, March, pp. 310–314.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Purdue School of Engineering and Technology, Indiana University Purdue University Indianapolis, 723W Michigan Street, Indianapolis, IN, 46202, USA

    Robert Meagher, Modukuri Sushmitha, Maher E. Rizkalla, Paul Salama & Mohamed El-Sharkawy

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  1. Robert Meagher
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  2. Modukuri Sushmitha
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  3. Maher E. Rizkalla
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  4. Paul Salama
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  5. Mohamed El-Sharkawy
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Correspondence to Maher E. Rizkalla.

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Meagher, R., Sushmitha, M., Rizkalla, M.E. et al. VHDL Design for Real Time Motion Estimation Video Applications. J Sign Process Syst Sign Image Video Technol 57, 339–348 (2009). https://doi.org/10.1007/s11265-008-0300-9

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  • DOI: https://doi.org/10.1007/s11265-008-0300-9

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