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The algorithm and VLSI architecture of a high efficient motion estimation with adaptive search range for HEVC systems

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Abstract

This paper presents a novel algorithm and VLSI architecture of motion estimation (ME) for high efficiency video coding systems. The proposed algorithm examines a much smaller set of search candidates and thus greatly reduces the computational complexity. Furthermore, in order to strike a balance between the quality of the Video and the efficiency of the system, this algorithm possesses the advantages that the number of search candidates is adaptive to the characteristic of the Video content. The simulation results show that, compared to the HM reference software, the proposed algorithm leads to a 96% reduction in search candidates with only 1.98% increment in average bitrate. Based on this algorithm, a hardware-efficient VLSI architecture of ME is designed and implemented with 90 nm technology. The experimental results show that, occupying the area complexity of 274.5 kGE, the presented design achieves 60 frames per second with resolution of 3840 × 2160 at the frequency of 201 MHz. The proposed ME system enhances the hardware efficiency by at least 50% compared to the prior works.

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Authors and Affiliations

  1. Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan, ROC

    Tzu-Ting Liao, Chung-An Shen & Yu-Hao Tseng

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  1. Tzu-Ting Liao
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  2. Chung-An Shen
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Correspondence to Chung-An Shen.

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Liao, TT., Shen, CA. & Tseng, YH. The algorithm and VLSI architecture of a high efficient motion estimation with adaptive search range for HEVC systems. J Real-Time Image Proc 16, 1943–1958 (2019). https://doi.org/10.1007/s11554-017-0697-0

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  • DOI: https://doi.org/10.1007/s11554-017-0697-0

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