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Tradeoff Between Complexity and Memory Size in the 3GPP Enhanced aacPlus Decoder: Speed-Conscious and Memory-Conscious Decoders on a 16-Bit Fixed-Point DSP

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Abstract

This paper investigates tradeoff between complexity and memory size (speed-memory tradeoff) in the 3GPP enhanced aacPlus decoder based on a 16-bit fixed-point DSP implementation. In order to investigate this tradeoff, the speed- and the memory-conscious decoders are implemented. The maximum number of operations for the implemented speed-conscious decoder is 29.3 million cycles per second (MCPS) for a 32 kb/s bitstream. The maximum number of operations for the memory-conscious decoder, where 70% of the data are allocated to an external memory area, increases by 5.7 MCPS (19%) for the bitstream. The investigation of this tradeoff provides an actual relationship between the computational complexity and the internal memory size of the 3GPP enhanced aacPlus decoder. This relationship is useful for implementing a decoder with a best speed–memory balance that is determined by each specific application and the user requirements.

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Notes

  1. Both the encoder and the decoder are standardized different from the MPEG standard that specifies only the decoder.

  2. Complexity of these bit streams was measured by the 3GPP fixed-point reference decoder [12]. The maximum numbers of operations were 32.2 and 34.6 wMOPS (weighed million operations per second) for the 48 kb/s and the 32 kb/s bit-streams, respectively. wMOPS is a measure of computational complexity on a virtual fixed-point DSP used in ETSI and ITU-T. The measured maximum wMOPS are almost equivalent to the maximum wMOPS shown in Annex A of [12]. Therefore, the prepared bit streams are suitable for the evaluation

References

  1. 3GPP. (2006). General audio codec audio processing functions; Enhanced aacPlus general audio codec; General description. TS 26.401

  2. ISO/IEC. (2004). Parametric coding for high-quality audio. ISO/IEC14496-3:2001/Amd 2:2004.

  3. Schuijers, E., et al. (2004). Low complexity parametric stereo coding. In the 116th AES Convention. Paper no. 6073.

  4. ISO/IEC. (2003). Bandwidth extension. ISO/IEC 14496-3:2001/Amd 1:2003.

  5. ISO/IEC. (2005). Listening test report on MPEG-4 High Efficiency AAC v2. ISO/IEC JTC 1/SC 29 /WG 11, N7137.

  6. ISO/IEC. (2001). Information technology—Coding of audio-visual objects—Part 3: Audio. ISO/IEC 14496-3:2001.

  7. Dietz, M., et al. (2002). Spectral band replication, a novel approach in audio coding. In the 112th AES Convention. Paper no. 5553.

  8. Shimada, O., et al. (2004). A Low Power SBR for the MPEG-4 Audio Standards and its DSP implementation. In the 116th AES Convention. Paper no. 6048.

  9. ISO/IEC. (2003). Report on the Verification Tests of MPEG-4 High Efficiency AAC. ISO/IEC JTC1/SC29/WG11, N6009.

  10. Texas Instruments. (2007). TMS320VC 5510/5510A Fixed-Point Digital Signal Processors. Texas Instruments SPRS076L.

  11. 3GPP. (2007). General audio codec audio processing functions; Enhanced aacPlus general audio codec; Floating-point ANSI-C code. TS 26.410.

  12. 3GPP. (2007). General audio codec audio processing functions; Enhanced aacPlus general audio codec; Fixed-point ANSI-C code. TS 26.411.

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Authors and Affiliations

  1. Common Platform Software Research Laboratories, NEC Corporation, 1753 Shimonumabe, Nakahara-ku, Kawasaki, 216-8666, Japan

    Osamu Shimada, Toshiyuki Nomura, Akihiko Sugiyama & Masahiro Serizawa

Authors
  1. Osamu Shimada
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  2. Toshiyuki Nomura
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  3. Akihiko Sugiyama
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  4. Masahiro Serizawa
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Correspondence to Osamu Shimada.

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Shimada, O., Nomura, T., Sugiyama, A. et al. Tradeoff Between Complexity and Memory Size in the 3GPP Enhanced aacPlus Decoder: Speed-Conscious and Memory-Conscious Decoders on a 16-Bit Fixed-Point DSP. J Sign Process Syst Sign Image Video Technol 57, 297–303 (2009). https://doi.org/10.1007/s11265-008-0285-4

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  • DOI: https://doi.org/10.1007/s11265-008-0285-4

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