Abstract
Multicore processors are becoming ubiquitous, and it is becoming increasingly common to run multiple real-time systems on a shared multicore platform. While this trend helps to reduce cost and to increase performance, it also makes it more challenging to achieve timing guarantees and functional isolation. One approach to achieving functional isolation is to use virtualization. However, virtualization also introduces many challenges to the multicore timing analysis; for instance, the overhead due to cache misses becomes harder to predict, since it depends not only on the direct interference between tasks but also on the indirect interference between virtual processors and the tasks executing on them. In this paper, we present a cache-aware compositional analysis technique that can be used to ensure timing guarantees of components scheduled on a multicore virtualization platform. Our technique improves on previous multicore compositional analyses by accounting for the cache-related overhead in the components’ interfaces, and it addresses the new virtualization-specific challenges in the overhead analysis. To demonstrate the utility of our technique, we report results from an extensive evaluation based on randomly generated workloads.
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Notes
A preliminary version of this paper has appeared in the Real-Time Systems Symposium (RTSS’13) (Xu et al. 2013).
In this work, we assume that the cores either do not share a cache, or that the shared cache has been partitioned into cache sets that are each accessed exclusively by one core (Kim et al. 2012) We believe that an extension to shared caches is possible, and we plan to consider it in our future work.
We are aware that using a constant maximum value to bound the cache-miss overhead of a task may be conservative, and extensions to a finer granularity, e.g., using program analysis, may be possible. However, as the first step, we keep this assumption to simplify the analysis in this work, and we defer such extensions to our future work.
We say that a compositional analysis method is compatible with the underlying component’s schedulability test it uses if whenever a component \(C\) with a taskset \(\tau \) is deemed schedulable on \(m\) cores by the schedulability test, then \(C\) is also deemed schedulable under an interface with bandwidth no larger than \(m\) by the compositional analysis method.
Here, \(d_k\) and \(t\) refer to \(D_k\) and \(A_k + D_k\) in Easwaran et al. (2009), respectively.
Note that the number of full processors is always bounded from below by \(\lfloor U_i \rfloor \), where \(U_i\) is the total utilization of the tasks in \(\mathcal {D}_i\), and bounded from above by the number of tasks in \(\mathcal {D}_i\) or the number of physical platform (if given), whichever is smaller.
Note that we inflate only the tasks’ WCETs and not the VCPUs’ budgets, since \(\delta ^{\mathsf {crpmd}}_{\mathsf {\tau _k}}\) includes the overhead for reloading the useful cache content of a preempted VCPU when it resumes.
Recall that \(\mathsf {LP}(\tau _k) = \{\tau _i | d_i > d_k\}\).
We assume other factors are same when we discuss one factor’s impact on the cache-aware analysis.
We note that the interfaces given by the hybrid method and the baseline method are the same as the interfaces given by the cache-aware hybrid analysis method and task-centric analysis method proposed in the conference version (Xu et al. 2013), respectively.
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Acknowledgments
This research was supported in part by the ONR N000141310802, NSF CNS-1329984, NSF CNS-1117185, NSF ECCS-1135630, and The Ministry of Knowledge Economy (MKE), Korea, under the Global Collaborative R&D program supervised by the KIAT (M002300089).
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Xu, M., Phan, L.T.X., Sokolsky, O. et al. Cache-aware compositional analysis of real-time multicore virtualization platforms. Real-Time Syst 51, 675–723 (2015). https://doi.org/10.1007/s11241-015-9223-2
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DOI: https://doi.org/10.1007/s11241-015-9223-2