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Parallel chaos-based image encryption algorithm: high-level synthesis and FPGA implementation

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A Publisher Correction to this article was published on 16 February 2024

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Abstract

Nowadays, establishing security in data transmission is essential, and it is achieved by cryptography. Encryption of still or video images in specific applications such as Internet of Things, medical and satellite imaging, in applications requiring high-speed encryption, or even in applications where a personal computer is unavailable or cannot be used needs special hardware. In this paper, an image encryption algorithm based on chaos theory named Parallel Chaotic Checksum-based Image Encryption or PCCIE algorithm is proposed that has been able to provide a fast, efficient and secure algorithm with a hardware perspective on the design and parallel system structure. Using high-level synthesis, PCCIE is implemented on a Field Programmable Gate Array (FPGA). The proposed algorithm using small and independent local image buffers solved FPGA internal memory limitation for encryption of large images. Ultimately, a Hexa-core crypto-processor with single-precision floating-point and fixed-point precision has been designed, capable of encrypting \(256 \times 256\) and Full HD images in 2.13 and 59.52 milliseconds, respectively, at 469 and 16 frames per second.

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Data Availability

Standard images such as Lena, Cameraman, and Peppers have been used to evaluate the algorithm and to compare with previous works. Algorithm simulation is done by MATLAB r2017a software. The design of the hardware algorithm, including the simulation and synthesis of the high-level code, has been done by Vivado 2018.3 software.

Change history

Notes

  1. Internet of Things.

  2. Personal Computer.

  3. Central Processing Unit.

  4. Graphics Processing Unit.

  5. Field Programmable Gate Array.

  6. 4th Order Runge Kutta.

  7. Advanced Encryption Standard.

  8. Programmable Logic.

  9. Processing System.

  10. Dynamic Random Access Memory.

  11. Block Random Access Memory.

  12. High-Level Synthesis.

  13. Finite-State Machine.

  14. Advanced eXtensible Interface.

  15. Parallel Chaotic Checksum-based Image Encryption.

  16. Peak signal-to-noise ratio.

  17. Number of Pixel Change Rate.

  18. Unified Average Changing Intensity.

  19. Intellectual Property.

  20. Lookup-Table.

  21. Flip-Flop.

  22. Digital Signal Processing.

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Funding

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Zanjan, Zanjan, Iran

    Saeed Sharifian Moghimi Moghaddam, Vahid Rashtchi & Ali Azarpeyvand

Authors
  1. Saeed Sharifian Moghimi Moghaddam
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  2. Vahid Rashtchi
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  3. Ali Azarpeyvand
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Contributions

SS: Design, implementation, manuscript, prepared figures. VR: Consulting in designing hardware, chaotic systems, manuscript (As Supervisor Professor) AA: Consulting in designing and verification of hardware implementation, manuscript (As Advisor Professor) All authors reviewed the manuscript.

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Correspondence to Vahid Rashtchi.

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The original online version of this article was revised: "In this article the author’s name Saeed Sharifian Moghimi Moghaddam was incorrectly written as M. M. Saeed Sharifian.”.

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Moghimi Moghaddam, S.S., Rashtchi, V. & Azarpeyvand, A. Parallel chaos-based image encryption algorithm: high-level synthesis and FPGA implementation. J Supercomput (2024). https://doi.org/10.1007/s11227-023-05784-1

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  • DOI: https://doi.org/10.1007/s11227-023-05784-1

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