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Vectorizing divergent control flow with active-lane consolidation on long-vector architectures

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Abstract

Control-flow divergence limits the applicability of loop vectorization, an important code-transformation that accelerates data-parallel loops. Control-flow divergence is commonly handled using an IF-conversion transformation combined with vector predication. However, the resulting vector instructions execute inefficiently with many inactive lanes. Branch-on-superword-condition-code (BOSCC) instructions are used to skip over some vector instructions, but their effectiveness decreases as vector length increases. This paper presents a novel vector permutation, Active-lane consolidation (ALC), that enables efficient execution of control-divergent loops by consolidating the active lanes of two vectors. This paper demonstrates the use of ALC with two loop transformations and applies them to kernels extracted from the SPEC CPU 2017 benchmark suite leading to up to a 30.9% reduction in dynamic instruction count compared to optimization using only BOSCCs. Motivated by ALC, this paper also proposes design changes to the ARM scalable vector extension (SVE) to improve vectorization of control-divergent loops.

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Notes

  1. For details of the experiment refer to Sect. 6.1.

  2. In this paper, vector registers are referred to simply as vectors.

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Acknowledgements

This research was funded by the University of Alberta Huawei Joint Innovation Collaboration (UAHJIC) and by the National Sciences and Engineering Research Council (NSERC) of Canada. We thank Giancarlo Pernudi Segura for his great assistance creating some of the assembly-level coding for the case studies.

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Authors and Affiliations

  1. University of Alberta, Edmonton, Canada

    Wyatt Praharenka, David Pankratz, João P. L. De Carvalho & José Nelson Amaral

  2. Huawei Technologies Canada, Markham, Canada

    Ehsan Amiri

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  1. Wyatt Praharenka
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  2. David Pankratz
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  3. João P. L. De Carvalho
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Correspondence to Wyatt Praharenka.

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Praharenka, W., Pankratz, D., De Carvalho, J.P.L. et al. Vectorizing divergent control flow with active-lane consolidation on long-vector architectures. J Supercomput 78, 12553–12588 (2022). https://doi.org/10.1007/s11227-022-04359-w

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