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AnyNoC: new network on a chip switching using the shared-memory and output-queue techniques for complex Internet of things systems

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Abstract

Recently, the Internet of things (IoT) has attracted a lot of attention owing to its versatile applications by enabling numerous things/objects to collect and exchange data via Internet. Despite the promising role of IoT, there exists the problem of integrating many heterogeneous functions into an embedded and complex IoT system. Meanwhile, in the past decade, we have also envisioned a paradigm shift in the embedded system market toward the system on a chip (SoC) by integrating all components into a single chip. But the on-chip communications of IoT systems remain an important and challenging issue. This work proposes a new network on a chip (NoC) switching, AnyNoC, employing the shared-memory and output-queue techniques implemented using the efficient dynamic link list, particularly suitable for the IoT SoC. The proposed high-level design can achieve the optimal performance by sharing the data buffer among all ports and eliminating the head-of-line blocking problem, resulting in a virtual point-to-point characteristic without the interruption of slow devices or congestion conditions in other ports. Moreover, the proposed architecture can minimize the required memory size by virtually sharing all buffers among all ports, resulting in one queue needed for each outbound port and totally N queues are required, where N denotes the number of ports. Therefore, compared to the famous wormhole switching, the proposed NoC architecture features lower cost and higher performance, which can approach the theoretical upper bound. Moreover, for a \(16\times 16\) network, the performance gain of the throughput of the proposed switching compared to the popular wormhole switching is about \(40\%\).

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Notes

  1. It will be shown later that the proposed design can outperform the popular wormhole technique under the constraint of the same buffer size. In another viewpoint, to achieve the same performance as the wormhole switching, the proposed design requires less buffer size.

  2. Ideally, each link can transmit one flit in every cycle.

References

  1. Xu Q, Aung KMM, Zhu Y, Yong KL (2016) Building a large-scale object-based active storage platform for data analytics in the internet of things. J Supercomput 72(7):2796–2814

  2. Chen S, Xu H, Liu D, Hu B, Wang H (2014) A vision of IoT: applications, challenges, and opportunities with China perspective. IEEE Internet of Things J 1(4):349–359

    Article  Google Scholar 

  3. ITRS Edition Reports (2011) http://public.itrs.net/reports.html

  4. Benini L, De Micheli G (2002) Network on chips: a new SoC paradigm. Computer 35(1):70–78. doi:10.1109/2.976921

  5. AMBA Specification Rev. 2.0 (1999) ARM Axis Sunnyvale, CA

  6. Specification for the: WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores. Revision: B.3, Released: 7 Sept 2002. https://opencores.org/cdn/downloads/wbspec_b3.pdf. Accessed 5 Apr 2017

  7. IBM Microelectronics (1999) CoreConnect bus architecture. IBM White Paper

  8. Kyeong KR, Eung S, Mooney VJ (2001) A comparison of five different multiprocessor SoC bus architectures. In: Proceedings of EUROMICRO Symposium Digital System Design, pp 202–209

  9. Bindal A, Mann S, Ahmed B, Raimundo L (2005) An undergraduate system-on-chip (SoC) course for computer engineering students. IEEE Trans Educ 48(2):279–289

    Article  Google Scholar 

  10. Tayan O (2009) Networks-on-chip: challenges, trends and mechanisms for enhancements. In: Proceedings of ICICT’09, pp 57–62

  11. Yu Z, Xiang D, Wang X (2015) Balancing virtual channel utilization for deadlock-free routing in torus networks. J. Supercomput. 71(1):3094–3115

    Article  Google Scholar 

  12. Diguet JP (2014) Self-adaptive network on chips. In: Proceedings of SBCCI’14, pp 1–6

  13. Nachiondo T, Flich J, Duato J (2006) Destination-based HoL blocking elimination. In: Proceedings of ICPADS’06, pp 1–10

Download references

Acknowledgements

This work is supported in part by the grant MOST 105-2221-E-006-019-MY2, Taiwan.

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Correspondence to Wen-Long Chin.

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Lin, JY., Hsieh, YT., Le, T.N. et al. AnyNoC: new network on a chip switching using the shared-memory and output-queue techniques for complex Internet of things systems. J Supercomput 74, 4470–4480 (2018). https://doi.org/10.1007/s11227-017-2035-5

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  • DOI: https://doi.org/10.1007/s11227-017-2035-5

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