Increasing frequency of functioning and decreasing transistor sizes in high performance logical circuits may result in illegal capacities, inductivities, resistances, and so on that generate decreasing estimated circuit frequency. These defects cannot be detected by physical methods. The main way of solving the problem is based on delay testing of logical circuits within the path delay fault (PDF) model. In this paper, facilities of enhancing PDF test sequence quality based on application of Reduced Ordered Binary Decision Diagrams (ROBDDs) that compactly represent all test pairs of neighbor test patterns for the circuit path are studied. Test patterns (Boolean vectors) are neighbor if they differ by only one component. It is established that using of these ROBDDs cut the lengths of test sequences by more than 1/3 in comparison with traditional scan test sequences simultaneously enhancing test sequence quality. In particular, we derive test sequences for robust testable PDFs of sequential circuits decreasing their power consumption and peak power values.
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References
A. Yu. Matrosova and V. B. Lipskiy, Avtom. Telemekh., No. 4, 135–148 (2015).
A. Yu. Matrosova, S. A. Ostanin, and V. Singh, Avtom. Telemekh.,No. 9, 126–142 (2013).
A. Yu. Matrosova, V. V. Andreeva, and E. A. Nikolaeva, Russ. Phys. J., 61, No. 5, 994–999 (2018).
P. Lindgren, M. Kerttu, M. Thornton, and R. Drechsler, in: Proc. 6th Asia and South Pacific Design Automation Conf. ASP-DAC 2001, Yokohama (2001), pp. 615–621.
R. S. Shelar and S. S. Sapatnekar, in: Proc. 7th Asia and South Pacific Design Automation Conf. ASP-DAC 2002, Bangalore (2002), pp. 87–92.
G. Gekas, D. Nikolos, E. Kalligeros, and X. Kavousianos, in: Proc. 12th IEEE Int. Conf. on Electronics, Circuits, and Systems, Gammarth (2005), pp. 1–4.
J. T. Tudu, E. Larsson, V. Singh, and V. D. Agrawal, in: Proc. 14th IEEE European Test Symposium ETS 2009, Sevilia (2009), pp. 25–30.
Z. Kotasek, J. Skarvada, and J. Strnadel, in: Proc. IEEE 13th Int. Symp. on Design and Diagnostics of Electronic Circuits and Systems, Vienna (2010), pp. 364–369.
V. Sunduja, S. Raghav, and J. P. Anita, in: Proc. Int. Conf. on Advances in Computing, Communications and Informatics ICACCI-2015, Kochi (2015), pp. 478–482.
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Translated from Izvestiya Vysshikh Uchebnykh Zavedenii, Fizika, No. 5, pp. 86–94, May, 2019.
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Matrosova, A.Y., Andreeva, V.V., Tychinskiy, V.Z. et al. Applying ROBDDs for Logical Circuit Delay Testing. Russ Phys J 62, 827–834 (2019). https://doi.org/10.1007/s11182-019-01784-y
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DOI: https://doi.org/10.1007/s11182-019-01784-y