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FPGA realizations of high-speed switching-type chaotic oscillators using compact VHDL codes

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Abstract

This paper introduces high-speed FPGA implementations of two different chaotic systems that rely on a switching-type nonlinearity. In particular, the single-switch Jerk system and the two-wing butterfly system (previously implemented only in analog form) are realized on a modular FPGA platform. For each system, two different hardware architectures are described: a parameters-independent architecture and a customized one with fixed parameters that utilizes less FPGA resources and thus has high throughput with the minimum number of clock cycles. Experimental results show that the parameters-independent architecture utilizes 70% more of the FPGA resources, while the customized one achieves a maximum clock frequency 172.5 MHz for the Jerk and 142.6 MHz for the two-wing system.

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This research did not receive any specific grant from funding agencies in the public, commercial, or not-for-profit sectors.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, College of Engineering, University of Sharjah, PO Box 27272, Sharjah, United Arab Emirates

    Talal Bonny & Ahmed S. Elwakil

  2. Nanoelectronics Integrated Systems Center (NISC), Nile University, Cairo, Egypt

    Ahmed S. Elwakil

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  1. Talal Bonny
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  2. Ahmed S. Elwakil
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Correspondence to Talal Bonny.

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Bonny, T., Elwakil, A.S. FPGA realizations of high-speed switching-type chaotic oscillators using compact VHDL codes. Nonlinear Dyn 93, 819–833 (2018). https://doi.org/10.1007/s11071-018-4229-7

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  • DOI: https://doi.org/10.1007/s11071-018-4229-7

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