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A Survey on Smart Optimisation Techniques for 6G-oriented Integrated Circuits Design

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Abstract

With the rapid development of next-generation wireless communications, there is a growing demand for high-quality integrated circuits (ICs), particularly analog ICs, which play a pivotal role for the full roll-out sixth-generation (6G) technology. So far, the IC design has been performed through manual approaches which sometimes results in time-consuming turnaround, especially the sizing phase of analog IC design. In order to make the IC design process much faster, recently automated methods for optimizing IC design has gained a lot of attention. From this perspective, this paper aims at providing a survey of the most recent works on optimization strategies for analog IC sizing, as well as a related categorization into two main categories: analytical methods and simulation-based methods. A further sub-classification within the realm of simulation-based methods is also provided by dividing the core mathematical principles into three major sub-methods: Bayesian-based, metaheuristic-based, and reinforcement-learning-based techniques. In addition, with the main aim of providing insights on the utilization of optimization algorithms for the IC sizing process, we present a case study involving the utilization of various metaheuristic algorithms in the design of a bandgap reference circuit - an essential analog IC component. The paper is concluded by highlighting potential future research directions in the field of analog IC design optimization and automation, which include exploration of multi-agent reinforcement learning, integration of quantum computing, and further development of full-flow automated tools for analog IC design.

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References

  1. Mercier PP, Calhoun BH, Wang P-HP, Dissanayake A, Zhang L, Hall DA, Bowers SM (2022) Low-power rf wake-up receivers: analysis, tradeoffs, and design. IEEE Open J Solid-State Circuits Soc 2:144–164

    Article  Google Scholar 

  2. Duong TQ, Nguyen LD, Narottama B, Ansere JA, Huynh DV, Shin H (2022) Quantum-inspired real-time optimization for 6G Networks: opportunities, challenges, and the road ahead. IEEE Open J Commun Soc 3:1347–1359

    Article  Google Scholar 

  3. Zhang F (2020) High-speed serial buses in embedded systems. Springer, Singapore

    Book  Google Scholar 

  4. Huang G, Hu J, He Y, Liu J, Ma M, Shen Z, Wu J, Xu Y, Zhang H, Zhong K, Ning X, Ma Y, Yang H, Yu B, Yang H, Wang Y (2021) Machine learning for electronic design automation: a survey. ACM Trans Des Autom Electron Syst 26:5

    Article  Google Scholar 

  5. Jiang W, Han B, Habibi MA, Schotten HD (2021) The road towards 6G: a comprehensive survey. IEEE Open J Commun Soc 2:334–366

    Article  Google Scholar 

  6. ITU-R (2015) IMT Traffic Estimates for the Years 2020 to 2030

  7. Viswanathan H, Mogensen PE (2020) Communications in the 6G era. IEEE Access 8:57063–57074

    Article  Google Scholar 

  8. Saad W, Bennis M, Chen M (2020) A vision of 6g wireless systems: applications, trends, technologies, and open research problems. IEEE Network 34(3):134–142

    Article  Google Scholar 

  9. Lambrechts JW, Sinha S, Sengupta K, Bimana A, Kadam S, Bhandari S, Preez JD, Shao Z, Huang X, Liu Z, Karahan EA, Blundo T, Allam M, Ghozzy S, Zhou J, Fang W, Valliarampath J (2024) Intelligent integrated circuits and systems for 5G/6G telecommunications. IEEE Access 12:21402–21419

    Article  Google Scholar 

  10. Rappaport TS, Xing Y, Kanhere O, Ju S, Madanayake A, Mandal S, Alkhateeb A, Trichopoulos GC (2019) Wireless communications and applications above 100 GHz: opportunities and challenges for 6g and beyond. IEEE Access 7:78729–78757

    Article  Google Scholar 

  11. Park B, Ji Y, Sim J-Y (2020) A 490-pW SAR temperature sensor with a leakage-based Bandgap-Vth Reference. IEEE Trans Circuits Syst I Exp Briefs 67(9):1549–1553

    Google Scholar 

  12. Homulle H, Sebastiano F, Charbon E (2018) Deep-Cryogenic Voltage References in 40-nm CMOS. IEEE Solid-State Circuits Lett. 1(5):110–113

    Article  Google Scholar 

  13. Yang X-S (2018) Optimization techniques and applications with examples, 1st edn. Wiley, Hoboken, NJ, USA

    Book  Google Scholar 

  14. Razavi B (2017) Design of analog CMOS integrated circuits, 2nd edn. McGraw-Hill Education, New York

    Google Scholar 

  15. Momoh J, Adapa R, El-Hawary M (1999) A review of selected optimal power flow literature to 1993. i. nonlinear and quadratic programming approaches. IEEE Trans Power Syst 14(1):96–104

  16. Momoh J, El-Hawary M, Adapa R (1999) A review of selected optimal power flow literature to 1993. ii. newton, linear programming and interior point methods. IEEE Trans Power Syst 14(1):105-111

    Article  Google Scholar 

  17. Kim J, Lee J, Vandenberghe L, Yang C-KK (2004) Techniques for improving the accuracy of geometric-programming based analog circuit design optimization. In: Proc. IEEE/ACM Int. Conf. Comput. Aided Design, San Jose, CA, USA, pp 863–870

  18. Lui S-H, Kwan H-K, Wong N (2010) Analog circuit design by nonconvex polynomial optimization: two design examples. Int J Circuit Theor Appl 38(1):25–43

    Article  Google Scholar 

  19. Wang Y, Orshansky M, Caramanis C (2014) Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization. In: Proc. ACM/IEEE Design Autom. Conf., San Francisco, CA, USA, pp 1–6

  20. Zhou R, Poechmueller P, Wang Y (2022) An analog circuit design and optimization system with rule-guided genetic algorithm. IEEE Trans Comput-Aided Design Integr Circuits Syst 41(12):5182–5192

    Article  Google Scholar 

  21. Tao J, Su Y, Zhou D, Zeng X, Li X (2019) Graph-constrained sparse performance modeling for analog circuit optimization via sdp relaxation. IEEE Trans Comput-Aided Design Integr Circuits Syst 38(8):1385–1398

    Article  Google Scholar 

  22. Fortes A, da Silva Jr LA, Domanski RA, Girard A (2019) Two-stage OTA sizing optimization using bio-inspired algorithms. J Integr Circuits Syst 14(3):1–10

    Article  Google Scholar 

  23. Vladimirescu A (1994) The SPICE book, 1st edn. John Wiley & Sons, New York, NY, USA

    Google Scholar 

  24. Sanabria-Borbón A, Soto-Aguilar S, Estrada-López J, Allaire D, Sánchez-Sinencio E (2020) Gaussian-process-based surrogate for optimization-aided and process-variations-aware analog circuit design. Electronics 9(4):685

    Article  Google Scholar 

  25. de Lima Moreto RA, Thomaz CE, Gimenez SP (2017) Gaussian fitness functions for optimizing analog cmos integrated circuits. IEEE Trans Comput-Aided Design Integr Circuits Syst 36(10):620–1632

    Article  Google Scholar 

  26. Chen C, Wang H, Song X, Liang F, Wu K, Tao T (2022) High-dimensional bayesian optimization for analog integrated circuit sizing based on dropout and gm/ID methodology. IEEE Trans Comput-Aided Design Integr Circuits Syst 41(11):4808–4820

    Article  Google Scholar 

  27. Zhang S, Yang F, Yan C, Zhou D, Zeng X (2022) An efficient batch-constrained bayesian optimization approach for analog circuit synthesis via multiobjective acquisition ensemble. IEEE Trans Comput-Aided Design Integr Circuits Syst 41(1):1–14

    Article  Google Scholar 

  28. Lu J, Li Y, Yang F, Shang L, Zeng X (2023) High-level topology synthesis method for \(|Delta\)-\(\Sigma \) modulators via bi-level bayesian optimization. IEEE Trans Circuits Syst I Exp Briefs 70(12):4389–4393

    Google Scholar 

  29. Lu J, Lei L, Huang J, Yang F, Shang L, Zeng X (2023) Automatic op-amp generation from specification to layout. IEEE Trans Comput-Aided Design Integr Circuits Syst 42(12):4378–4390

    Article  Google Scholar 

  30. Choi M, Choi Y, Lee K, Kang S (2023) Reinforcement learning-based analog circuit optimizer using gm/id for sizing. In: Proc. ACM/IEEE Design Autom. Conf., San Francisco, CA, USA, pp 1–6

  31. Gu T, Li W, Zhao A, Bi Z, Li X, Yang F, Yan C, Hu W, Zhou D, Cui T, Liu X, Zhang Z, Zeng X (2024) Bbgp-sdfo: Batch bayesian and gaussian process enhanced subspace derivative free optimization for high-dimensional analog circuit synthesis. IEEE Trans Comput-Aided Design Integr Circuits Syst 43(2):417–430

    Article  Google Scholar 

  32. Yang X-S, Deb S, Loomes M, Karamanoglu M (2013) A framework for self-tuning optimization algorithm. Neural Comput Appl 23:2051–2057

    Article  Google Scholar 

  33. Gielen G, Walscharts H, Sansen W (1990) Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE J Solid-State Circuits 25(3):707–713

    Article  Google Scholar 

  34. Das P, Jajodia B (2022) Design automation of two-stage operational amplifier using multi-objective genetic algorithm and spice framework. In: Proc Nepal, Int Conf Inventive Comput Tech pp 166–170

  35. Taherzadeh-Sani M, Lotfi R, Zare-Hoseini H, Shoaei O (2003) Design optimization of analog integrated circuits using simulation-based genetic algorithm. In: Proc. Int. Stmp. Signals, Circuits Syst., vol. 1, Iasi, Romania, pp 73–76

  36. Kchaou OB, Sallem A, Pereira P, Fakhfakh M, Fino MH (2015) Multi-objective sensitivity-based optimization of analog circuits exploiting nsga-ii front ranking. Proc Int Conf Synth Model Anal Simul Methods Appl Circuit Design 1–4

  37. Li Y, Wang Y, Li Y, Zhou R, Lin Z (2020) An artificial neural network assisted optimization system for analog design space exploration. IEEE Trans Comput-Aided Design Integr Circuits Syst 39(10):2640–2653

    Article  Google Scholar 

  38. Delwar TS, Siddique A, Aras U, Ryu JY (2024) A design of adaptive genetic algorithm-based optimized power amplifier for 5G applications. Circuits Syst Signal Process 43:2–21

    Article  Google Scholar 

  39. Rashid R, Nambath N (2022) Area optimisation of two stage Miller compensated Op-Amp in 65 nm Using Hybrid PSO. IEEE Trans Circuits Syst I Exp Briefs 69(1):199–203

    Google Scholar 

  40. Raj A, Majumder S, Mishra GP (2023) Design of a CMOS based ring VCO using particle swarm optimisation. Analog Integr Circ Signal Process

  41. Rashid R, Nambath N (2021) Hybrid particle swarm optimization algorithm for area minimization in 65 nm Technology. In: Proc IEEE Int Symp Circuits Syst, Daegu, (South) Korea, pp 1–5

  42. Shreeharsha KG, Siddharth RK, Vasantha MH, Kumar YBN (2023) Partition bound random number-based particle swarm optimization for analog circuit sizing. IEEE Access 11:123577–123588

    Article  Google Scholar 

  43. Fayazi M, Taba MT, Afshari E, Dreslinski R (2023) AnGeL: fully-automated analog circuit generator using a neural network assisted semi-supervised learning approach. IEEE Trans Circuits Syst I Reg Papers 70(11):4516–4529

    Article  Google Scholar 

  44. Hoang T, Quoc TN, Zhang L, Duong TQ (2023) Novel methods for improved particle swarm optimization in designing the Bandgap reference circuit. IEEE Access 11:139964–139978

    Article  Google Scholar 

  45. Fortes A, da Silva LA, Girardi A (2018) Low power bulk-driven OTA design optimization using cuckoo search algorithm. In: Proc. Symp. Integr. Circuits Syst. Design, Ben Goncalves, Brazi, pp 1–7

  46. Li C, You F, Yao T, Wang J, Shi W, Peng J, He S (2021) Simulated annealing particle swarm optimization for high-efficiency power amplifier design. IEEE Trans Microw Theory Tech 69(5):2494–2505

    Article  Google Scholar 

  47. Joshi D, Dash S, Malhotra A, Sai PV, Das R, Sharma D, Trivedi G (2017) Optimization of 2.4 ghz cmos low noise amplifier using hybrid particle swarm optimization with lévy flight. In Proc Int Conf VLSI Design and Proc Int Conf Embedded Syst, Hyderabad, India, pp 181–186

  48. Barari M, Karimi HR, Razaghian F (2014) Analog circuit design optimization based on evolutionary algorithms. Math Problems Eng 2014

  49. Phelps R, Krasnicki M, Rutenbar R, Carley L, Hellums J (2000) Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search. IEEE Trans Comput-Aided Design Integr Circuits Syst 19(6):703–717

    Article  Google Scholar 

  50. Wang X, Wang S, Liang X, Zhao D, Huang J, Xu X, Dai B, Miao Q (2022) Deep reinforcement learning: A survey. IEEE Trans Neural Netw Learn Syst 1–15

  51. Settaluri K, Haj-Ali A, Huang Q, Hakhamaneshi K, Nikolic B (2020) Autockt: Deep reinforcement learning of analog circuit designs. In: Proc. Design, Automat. Test Europe Conf. Exhibit., Grenoble, France, pp 490–495

  52. Settaluri K, Liu Z, Khurana R, Mirhaj A, Jain R, Nikolic B (2022) Automated design of analog circuits using reinforcement learning. IEEE Trans Comput-Aided Design Integr Circuits Syst 41(9):2794–2807

    Article  Google Scholar 

  53. Wang H, Yang J, Lee H-S, Han S (2018) Learning to design circuits. In: Proc Conf Neural Inf Process Syst Montreal, Canada

  54. Wang H, Wang K, Yang J, Shen L, Sun N, Lee H-S, Han S (2020) GCN-RL circuit designer: transferable transistor sizing with graph neural networks and reinforcement learning. In: Proc. ACM/IEEE Design Autom. Conf., San Francisco, CA, USA, pp 1–6

  55. Li Z, Carusone AC (2023) Design and optimization of low-dropout voltage regulator using relational graph neural network and reinforcement learning in open-source SKY130 Process. In: Proc San Francisco, CA, USA, Oct, IEEE/ACM Int Conf Comput Aided Design pp 01–09

  56. Hong J, Kim S, Jeon D (2022) An automatic circuit design framework for level shifter circuits. IEEE Trans Comput-Aided Design Integr Circuits Syst 41(12):5169–5181

    Article  Google Scholar 

  57. Barth-Maron G, Hoffman MW, Budden D, Dabney W, Horgan D, TB D, Muldal A, Heess N, Lillicrap T (2018) Distributed distributional deterministic policy gradients. [Online]. Available: https://arxiv.org/abs/1804.08617

  58. Jiang S, Zhang C, Wu W, Chen S (2019) Combined economic and emission dispatch problem of wind-thermal power system using gravitational particle swarm optimization algorithm. Math Prob Eng

  59. Yu C, Velu A, Vinitsky E, Gao J, Wang Y, Bayen A, Wu Y (2022) The surprising effectiveness of PPO in Cooperative Multi-Agent Games. In: Proc Conf Neural Inf Process Syst, New Orleans, LA, USA

  60. Duong TQ, Ansere JA, Narottama B, Sharma V, Dobre OA, Shin H (2022) Quantum-inspired machine learning for 6G: fundamentals, security, resource allocations, challenges, and future research directions. IEEE Open J Veh Technol 3:375–387

  61. Nakahara M, Ohmi T (2008) Quantum computing?: from linear algebra to physical realizations. CRC Press, USA

    Book  Google Scholar 

  62. McGeoch CC (2014) Adiabatic quantum computation and quantum annealing. Springer Cham, Switzerland

    Book  Google Scholar 

  63. Ansere JA, Duong TQ, Khosravirad SR, Sharma V, Masaracchia A, Dobre OA (2023) Quantum deep reinforcement learning for 6g mobile edge computing-based IoT systems. In: Proc Marrakesh Morocco, Jul, Int Wireless Commun Mobile Comput, pp 406–411

  64. Ansere JA, Tran DT, Dobre OA, Shin H, Karagiannidis GK, Duong TQ (2024) Energy-efficient optimization for mobile edge computing with quantum machine learning. IEEE Wireless Comm Lett 13(3):661–665

    Article  Google Scholar 

  65. Ansere JA, Gyamfi E, Sharma V, Shin H, Dobre OA, Duong TQ (2023) Quantum deep reinforcement learning for dynamic resource allocation in mobile edge computing-based IoT systems. IEEE Trans Wireless Commun 1–1

  66. Fang P-H, Chen Y-S, Wu J-S, Yu P (2024) Inverse reticle optimization with quantum annealing and hybrid solvers. IEEE Access 12:33069–33078

    Article  Google Scholar 

  67. Zhao Z, Zhang L (2022) Deep reinforcement learning for analog circuit structure synthesis. In: Proc. Design, Automat. Test Europe Conf. Exhibit., Antwerp, Belgium, pp 1157–1160

  68. Zhao Z, Zhang L (2022) Analog integrated circuit topology synthesis with deep reinforcement learning. IEEE Trans Comput-Aided Design Integr Circuits Syst 41(12):5138–5151

    Article  Google Scholar 

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Acknowledgements

The work of Trang Hoang was supported by Vietnam National University Ho Chi Minh City (VNU-HCM) under Grant DS2023-20-03. The work of T. Q. Duong was supported in part by the Canada Excellence Research Chair (CERC) Program CERC-2022-00109.

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T. Q. Nguyen: writing the original draft; T. Hoang and T. Q. Duong: conceptualization; T. Hoang, L. Zhang, O. Dobre, and T. Q. Duong: editing, supervision. All authors reviewed the manuscript.

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Correspondence to Trang Hoang.

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Nguyen, T.Q., Hoang, T., Zhang, L. et al. A Survey on Smart Optimisation Techniques for 6G-oriented Integrated Circuits Design. Mobile Netw Appl (2024). https://doi.org/10.1007/s11036-024-02343-7

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