Skip to main content
SpringerLink
Log in

On the optimization of molding warpage for wafer-level glass interposer packaging

  • Published:
Journal of Materials Science: Materials in Electronics Aims and scope Submit manuscript

Abstract

Through-glass-via (TGV) technology has great potential for various applications in advanced electronic packaging and integrated passive devices due to its excellent electrical/optical properties, favorable mechanical stability and low cost. Nonetheless, the manufacturing of TGV packages is often impeded by molding warpage, which is caused by the large coefficient of thermal expansion (CTE) mismatches among packaging materials such as semiconductors, metals, and molding compounds. This warpage not only creates troubles in subsequent manufacturing processes but also degrades the performance and reliability of the final devices or packages. This study investigated the characteristics of warpage during molding process by finite element simulations and experiments for the state-of-the-art 2.5D glass interposer packages. A cell model was established to homogenize the micro-bumps, underfill, and the re-distribution layers (RDLs) for simplifying the package structure. A wafer-level glass interposer packaging process based on TGV and molding was proposed. The warpage values were measured by a laser-assisted method, and the simulated values agreed well with the experimental measurements. Furthermore, the effect of different molding and glass materials on warpage was explored. This study provided a viable approach to predict the wafer-level molding warpage and optimize process parameters to reduce warpage and improve packaging reliability.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

Data availability

The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.

References

  1. C. Xu, P. Sun, Z. Liu, J. Liu, Wafer Compression Molding Warpage Optimization for Wafer Level Package, in 2020 IEEE 21st International Conference on Electronic Packaging Technology, (2020)

  2. J. Zhao, F. Qin, D. Yu, Z. Chen, S. Zhao, Warpage Characteristic of Glass Interposer with Different CTE's and Thickness, in 2021 IEEE 22nd International Conference on Electronic Packaging Technology, (2021)

  3. J.H. Lau, TSV Manufacturing Yield and Hidden Costs for 3D IC Integration, in 2010 IEEE 60th Electronic Components and Technology Conference, (2010)

  4. A.L. Manna, T. Buisson, M. Detalle, K. J. Rebibis, D. Velenis, W. Zhang, E. Beyne, Challenges and Improvements for 3D-IC Integration Using Ultra Thin (25μm) Devices, in 2012 IEEE 62nd Electronic Components and Technology Conference, (2012)

  5. C.C. Lee, C. Hung, C. Cheung, P.F. Yang, C.L. Kao, D.L. Chen, M.K. Shih, C.L.C. Chien, Y.H. Hsiao, L.C. Chen, M. Su, M. Alfano, J. Siegel, J. Din, B. Black, An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer, in 2016 IEEE 66th Electronic Components and Technology Conference, (2016)

  6. R. Dunne, Y. Takahashi, K. Mawatari, M. Matsuura, T. Bonifield, P. Steinmann, D. Stepnia, Development of a Stacked WCSP Package Platform Wsing TSV (Through Silicon Via) Technology, in 2012 IEEE 62nd Electronic Components and Technology Conference, (2012)

  7. S.L. Tang, G.L. Zhao, Y.H. Xue, H. Yuan, Y.J. Yang, High density assembly and packaging technology based on flip-chip on TSV and chip stacking. Electronics & Packaging. 22(8), 080201 (2022)

    Google Scholar 

  8. M. Shih, K. Chen, T. Lee, D. Tarng, C.P. Hung, FE simulation model for warpage evaluation of glass interposer substrate packages. IEEE Transac. Compon. Packag. Manuf. Technol. 11(4), 690–696 (2021)

    Article  Google Scholar 

  9. L. Chen, D. Yu, Investigation of low-cost through glass vias formation on borosilicate glass by picosecond laser-induced selective etching. J. Mater. Sci.: Mater. Electron. 32(12), 16481–16493 (2021)

    Google Scholar 

  10. H. Cai, J. Yan, S. Ma, R.F. Luo, J. Chen, Design, fabrication, and radio frequency property evaluation of a through-glass-via interposer for 2.5D radio frequency integration. J. Micromech. Microeng. 29(7), 075002 (2019)

    Article  CAS  Google Scholar 

  11. V. Sukumaran, T. Bandyopadhyay, V. Sundaram, R. Tummala, Low-cost thin glass interposers as a superior alternative to silicon and organic interposers for packaging of 3-D ICs. IEEE Transac. Compon. Packag. Manuf. Technol. 2(9), 1426–1433 (2012)

    Article  CAS  Google Scholar 

  12. H.Y. Peng, M. Devarajan, T.T. Lee, D. Lace, Comparison of radio frequency and microwave plasma treatments on LED chip bond pad for wire bond application. IEEE Transac. Compon. Packag. Manuf. Technol. 5(4), 562–569 (2015)

    Article  CAS  Google Scholar 

  13. J. Miremadi, Impact of PBGA-Ball-Coplanarity on Formation of Solder Joints, in 1995 IEEE 45th Electronic Components and Technology Conference, (1995)

  14. F. Qin, S. Zhao, Y. Dai, M. Yang, M. Xiang, D. Yu, Study of warpage evolution and control for six-side molded WLCSP in different packaging processes. IEEE Transac. Compon. Packag. Manuf. Technol. 10(4), 730–738 (2020)

    Article  Google Scholar 

  15. A. Benali, M. Faqir, M. Bouya, A. Benabdellah, M. Ghogho, Analytical and finite element modeling of through glass via thermal stress. Microelectronic Engineering. 151, 12–18 (2016)

    Article  CAS  Google Scholar 

  16. H.-C. Cheng, Z.-D. Wu, Y.-C. Liu, Viscoelastic warpage modeling of fan-out wafer-level packaging during wafer-level mold cure process. IEEE Transac. Compon. Packag. Manuf. Technol. 10(7), 1240–1250 (2020)

  17. T. An, F. Qin, W. Wu, D. Yu, L. Wan, J. Wang, An Equivalent Model of TSV Silicon Interposer, in 2012 IEEE 13rd International Conference on Electronic Packaging Technology & High Density Packaging, (2012)

  18. J. Gu, C.T. Lim, A. Tay, Simulation of Mechanical Response of Solder Joints Under Drop Impact Using Equivalent Layer Models, in 2005 IEEE 55th Electronic Components and Technology Conference, (2005)

  19. M.-K. Shih, Y.-W. Huang, G.-S. Lin, Next-generation high-density PCB development by fan-out RDL technology. IEEE Trans. Device Mater. Reliab. 22(2), 296–305 (2022)

    Article  CAS  Google Scholar 

  20. W. Li, D. Yu, Experimental and numerical investigations of the warpage of fan-out wafer-level packaging with SAW filters. IEEE Transac. Compon. Packag. Manuf. Technol. 12(5), 869–877 (2022)

    Article  CAS  Google Scholar 

  21. K.X. Hu, C.P. Yeh, B. Doot, A.F. Skipor, K.W. Wyat, Die Cracking in Flip-Chip-on-Board Assembly, in 1995 IEEE 45th Electronic Components and Technology Conference, (1995)

  22. E. Suhir, Predicted bow of plastic packages of integrated circuit (IC) devices. Journal of Reinforced Plastics & Composites. 12(9), 951–972 (1993)

  23. F. Yang, S.A. Meguid, Efficient multi-level modeling technique for determining effective board drop reliability of PCB assembly. Microelectronics Reliability. 53(7), 975-984 (2013)

  24. D.R. Kiran, Total Quality Management[M]. (2017)

Download references

Acknowledgements

This Research is supported by the National Natural Science Foundation of China (Grant Nos. 61974121, U2241222, 62104206) and the Fundamental Research Funds for the Central Universities (Grant No. 20720220072).

Funding

National Natural Science Foundation of China,62104206, Yi Zhong,U2241222,Daquan Yu, 61974121,Daquan Yu, Fundamental Research Funds for the Central Universities, 20720220072, Yi Zhong

Author information

Authors and Affiliations

  1. School of Electronic Science and Engineering, Xiamen University, Xiamen, 361005, China

    Shuchao Bao, Wei Li, Yi Zhong & Daquan Yu

  2. School of Materials Science and Engineering, Xiamen University of Technology, Xiamen, 361005, China

    Yimin He

  3. Xiamen Sky Semiconductor Technology Co., Ltd, Xiamen, 361005, China

    Long Zhang & Daquan Yu

Authors
  1. Shuchao Bao
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Wei Li
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yimin He
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Yi Zhong
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Long Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Daquan Yu
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

All authors contributed to the study conception and design. Material preparation, data collection and analysis were performed by SB, WL, YH, YZ, LZ and DY. The first draft of the manuscript was written by SB and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.

Corresponding authors

Correspondence to Yi Zhong or Daquan Yu.

Ethics declarations

Competing interests

This work was supported by the National Natural Science Foundation of China (Grant Nos. 61974121, U2241222, 62104206), Science and the Fundamental Research Funds for the Central Universities (Grant No. 20720220072). The authors declare they have no financial interests.

Research involving human and animal participants

This research does not involve Human Participants and/or Animals.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Bao, S., Li, W., He, Y. et al. On the optimization of molding warpage for wafer-level glass interposer packaging. J Mater Sci: Mater Electron 34, 1061 (2023). https://doi.org/10.1007/s10854-023-10475-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s10854-023-10475-x

Search

Navigation