Abstract
2.5D interposer technology has gotten a lot of attention as a viable solution to high IO density, cost, and performance challenges. Glass is a potential choice as an interposer material in an integrated package, with low dielectric loss and simple processing, it can be a low-cost alternative to silicon interposer. In this paper, a 2.5D package using glass interposer with a size of 10 mm × 15 mm × 0.8 mm is developed. The interposer with through glass via (TGV) technology simplifies the process and dramatically reduces manufacturing costs, which is especially important for the system in package. Several key processes are developed and discussed. To optimize the wafer level warpage problem, finite element modeling is used to simulate the warpage of glass wafers and optimize the process parameters and material parameters. Finally, the package level reliability tests are conducted on the 2.5D packages, after pro-conditional level 3 and temperature cycling tests, and the final packages pass the reliability tests without significant failure mode, which provides an important reference value for the subsequent mass-production of the TGV interposer.
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The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.
References
X. Zhang, J.K. Lin, S. Wickramanayaka et al., Heterogeneous 2.5D integration on through silicon interposer. Appl. Phys. Rev 2(2), 021308 (2015)
H. Jeong, K.H. Jung, C.J. Lee et al., Effect of epoxy mold compound and package dimensions on the thermomechanical properties of a fan-out package. J. Mater. Sci. Mater. Electron. (2020). https://doi.org/10.1007/s10854-020-03243-8
P. Lianto, C.W. Tan, Q.J. Peng et al., Fine-pitch rdl integration for fan-out wafer-level packaging[C]// 2020 IEEE 70th electronic components and technology conference (ECTC). IEEE, 2020
Z. Chen, D. Yu, M. Zhang, F. Jiang, Development and reliability study of 3-D wafer level packaging for SAW filter using thin film capping. IEEE Trans. Compon. Packag. Manuf. Technol. 11(7), 1047–1054 (2021). https://doi.org/10.1109/TCPMT.2021.3091998
F. Yang, G. Han, J. Yang et al., Research on wafer-level MEMS packaging with through-glass vias. Micromachines 10(1), 15 (2018)
Z.H.A.O. Jin, L.I. Wei, Z.H.O.N.G. Yi, Y.U. Daquan, Q.I.N. Fei, Stress issues in 3D interconnect technology using through Glass Vias. J. Mech. Eng. 58(2), 246–258 (2022)
K. Demir, V. Sukumaran, Y. Sato et al., Reliability of fine-pitch through-vias in glass interposers and packages for high-bandwidth computing and communications. Mater. Sci. Mater. Electron. 29, 12669–12680 (2018)
A. Usman et al., Interposer technologies for high-performance applications. IEEE Trans. Compon. Packag. Manuf. Technol. 7(6), 819–828 (2017). https://doi.org/10.1109/TCPMT.2017.2674686
Z. Chen, D. Yu, F. Jiang, Development of 3-D wafer level packaging for SAW filters using thin glass capping technology. IEEE Trans. Compon. Packag. Manuf. Technol. 12(2), 375–381 (2022). https://doi.org/10.1109/TCPMT.2022.3140863
M. Lueck, A. Huffman, A. Shorey, Through glass vias (TGV) and aspects of reliability. Proc. Electron. Compon. Technol. Conf. 2015, 672–677 (2015)
Z. Chen, D. Yu, Y. Zhong, Development of 3D wafer level hermetic packaging with through glass vias (TGVs) and transient liquid phase bonding technology for RF filter. Sensors 22, 2114 (2022)
C. Zhu, W. Ning, H. Lee et al., Experimental identification of warpage origination during the wafer level packaging process. Proceedings-electronic components and technology conference, 815–820 2014
S. Gao, Z. Dong, R. Kang et al., Warping of silicon wafers subjected to back-grinding process. Precis. Eng. 40(1), 87–93 (2015)
J.H. Lau et al., Warpage and thermal characterization of fan-out wafer-level packaging. IEEE Trans. Compon. Packag. Manuf. Technol. 7(10), 1729–1738 (2017). https://doi.org/10.1109/TCPMT.2017.2715185
J.H. Lau et al., Warpage measurements and characterizations of fan-out wafer-level packaging with large chips and multiple redistributed layers. IEEE Trans. Compon. Packag. Manuf. Technol. 8(10), 1729–1737 (2018). https://doi.org/10.1109/TCPMT.2018.2848666
H. Cheng, Z. Wu, Y. Liu, Viscoelastic warpage modeling of fan-out wafer-level packaging during wafer-level mold cure process. IEEE Trans. Compon. Packag. Manuf. Technol. 10(7), 1240–1250 (2020). https://doi.org/10.1109/TCPMT.2020.2992041
O. Ahmed, C. Okoro, S. Pollard et al., The effect of materials and design on the reliability of through-glass vias for 2.5D integrated circuits: a numerical study. J. Multidiscip. Model. Mater. Struct. 17, 451–464 (2021)
M. Shih, K. Chen, T. Lee, D. Tarng, C.P. Hung, Simulation model for warpage evaluation of glass interposer substrate packages. IEEE Trans. Compon. Packag. Manuf. Technol. 11(4), 690–696 (2021)
M. Shih, C.-Y. Huang, T.-H. Chen, C.-C. Wang, D. Tarng, C.P. Hung, Electrical, thermal, and mechanical characterization of eWLB, fully molded fan-out package, and fan-out chip last package. IEEE Trans. Compon. Packag. Manuf. Technol. 9(9), 1765–1775 (2019). https://doi.org/10.1109/TCPMT.2019.2935477
F. Qin, S. Zhao, Y. Dai, M. Yang, M. Xiang, D. Yu, Study of warpage evolution and control for six-side molded WLCSP in different packaging processes. IEEE Trans. Compon. Packag. Manuf.Technol. 10(4), 730–738 (2020). https://doi.org/10.1109/TCPMT.2020.2975571
Y. Mengke, Q. Fei, Y. Daquan., Numerical simulation on wafer warpage during molding process of WLCSP,“ 2018 19th International conference on electronic packaging technology (ICEPT), pp. 886–890, 2018 https://doi.org/10.1109/ICEPT.2018.8480570
C. Zhu, P. Guo, Z. Dai., Investigation on wafer warpage evolution and wafer asymmetric deformation in fan-out wafer level packaging processes,“ 2017 18th International conference on electronic packaging technology (ICEPT), pp. 664–668, 2017 https://doi.org/10.1109/ICEPT.2017.8046539
Acknowledgements
This Research is supported by the National Natural Science Foundation of China (Grant Nos. 6197412). We gratefully thank the great support from the engineering teams within Xiamen Sky Semiconductor Technology Co., Ltd.
Funding
National Natural Science Foundation of China, 61974121, Daquan Yu.
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Conceptualization and patent, JZ and FQ; investigation, JZ and ZC; package structure design and fabrication, JZ and DY; reliability analysis, JZ; writing—original draft preparation, JZ; writing—review and editing, FQ, DY and ZC; supervision, DY; project administration, DY All authors have read and agreed to the published version of the manuscript. All authors read and approved the final manuscript.
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This work was supported by the National Natural Science Foundation of China (Grant No. 61974121).
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Zhao, J., Chen, Z., Qin, F. et al. Development of high performance 2.5D packaging using glass interposer with through glass vias. J Mater Sci: Mater Electron 34, 1790 (2023). https://doi.org/10.1007/s10854-023-11185-0
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DOI: https://doi.org/10.1007/s10854-023-11185-0