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Solution processed low-voltage metal-oxide transistor by using TiO2/Li–Al2O3 stacked gate dielectric

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Abstract

A solution processed top-contact bottom-gated SnO2 thin-film transistor (TFT) has been fabricated using a TiO2/Li–Al2O3 bilayer stacked gate dielectric that show operating voltage of this TFT within 2.0 V. It is observed that the bilayer dielectric has much higher areal capacitance with lower leakage current density that significantly improve the overall device performance of TFT. The TFT with bilayer gate dielectric shows an effective carrier mobility (μsat) of 9.2 cm2 V−1 s−1 with an on/off ratio of 7.1 × 103 which are significantly higher with respect to the TFT with a single layer Li–Al2O3 gate dielectric. The origin of this improvement is due to the Schottky junction between the highly doped silicon (p++-Si) and TiO2 of bilayer stacked dielectric that induced electrons to the channel which reduces the dielectric/semiconductor interface trap-state. This investigation opens a new path to develop TFT device performance using a suitable bilayer stack of gate dielectric.

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Data availability

The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

This work was supported by the "Science and Engineering Research Board," India (Grant No. EMR/2015/000689). The authors are grateful to the Central Instrument Facility Centre, IIT (BHU), for providing the AFM measurement facility. Nila Pal thanks DST-SERB for providing SRF fellowship, and Utkarsh Pandey thanks IIT (BHU) for providing Ph.D. fellowship.

Funding

Funding was provided by Science and Engineering Research Board (Grant Nos. CRG/2019/001826 and EMR/2015/000689).

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Authors and Affiliations

  1. School of Materials Science and Technology, Indian Institute of Technology (Banaras Hindu University), Varanasi, 221005, India

    Nila Pal, Utkarsh Pandey & Bhola N. Pal

  2. Organic Electronic Research Centre and Department of Electronic Engineering, Ming-Chi University of Technology, New Taipei City, 243, Taiwan

    Sajal Biring & Bhola N. Pal

Authors
  1. Nila Pal
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  2. Utkarsh Pandey
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  3. Sajal Biring
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  4. Bhola N. Pal
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Contributions

NP did most of the experimental research work, manuscript writing, data analysis. UP did partial experimental research work and data analysis. SB gave some measurement facilities and jointly figure out the outline of this work. BNP supervise this research work.

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Correspondence to Sajal Biring or Bhola N. Pal.

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Pal, N., Pandey, U., Biring, S. et al. Solution processed low-voltage metal-oxide transistor by using TiO2/Li–Al2O3 stacked gate dielectric. J Mater Sci: Mater Electron 33, 9580–9589 (2022). https://doi.org/10.1007/s10854-021-07581-z

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  • DOI: https://doi.org/10.1007/s10854-021-07581-z

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