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Impact of packaging materials on reliability test for low-K wire bond-stacked flip chip CSP

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Abstract

As the consumer electronics market keeps expanding, the system-in-package (SiP) has become more and more popular. The SiP has the benefits of space efficiency and an integrated flexible function by stacking different function dies in a single package. With die stacking, bi-material interfacial delamination becomes a primary concern of reliability testing. This work evaluates the impact of encapsulated molding compound (EMC) and underfill material on the reliability test for the low-K wire bond-stacked flip chip CSP (WB-sFC CSP). The CSP packaging size is 16 × 16 × 1.2 mm with a 4 × 5 × 0.15 mm low-K wire bond die stacked on a low-K 8 × 8 × 0.15 mm flip chip die. The reliability testing condition is JEDEC MSL 2a (reflow peak temperature is 260 °C) followed by the temperature cycling test (TCT, −55 to 125 °C) of 1000 cycles. The severe pre-conditioning environment makes the packaging materials selection a challenge. Delamination between the interface of the underfill and other packaging components leads to premature failure during preconditioning. TCT stress also induces delamination between the interface of the backside of the bottom die and the encapsulated molding compound. Initially, the EMC selection was decided by the first stage experimental result based on the assembly yield. A DOE was performed to study the effect of underfill property on the packaging stress using the finite element analysis (FEA). According to the FEA results, the trend of underfill property selection for solving the underfill delamination and the backside of the bottom die delamination were in conflict. The low coefficient of thermal expansion (CTE) and the high Young’s modulus (E) underfill can reduce the stress located at the backside of the bottom die corner but it will increase the underfill stress. Plasma cleaning was applied to improve the underfill and the packaging components interface bond strength prior to dispensing the underfill. In the second stage, three underfills were evaluated based on the three different reasons, low modulus for preventing underfill delamination, high modulus for reducing the backside of the bottom die stress, and low moisture absorption by reducing steam pressure during preconditioning. The experimental results in this work demonstrate that only a high modulus underfill can pass the reliability test.

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Acknowledgement

The author would like to thank Joe Lin and Kevin Tsai from Siliconware Precision Industries Co., Ltd for their assembly support.

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Correspondence to K. M. Chen.

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Chen, K.M. Impact of packaging materials on reliability test for low-K wire bond-stacked flip chip CSP. J Mater Sci: Mater Electron 20, 484–489 (2009). https://doi.org/10.1007/s10854-008-9756-4

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  • DOI: https://doi.org/10.1007/s10854-008-9756-4

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