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Experimental measurement of the effect of copper through-silicon via diameter on stress buildup using synchrotron-based X-ray source

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Abstract

In this work, the effect of copper through-silicon via (TSV) interconnect diameter on stress buildup in Cu TSVs was experimentally determined using a synchrotron-based X-ray microdiffraction technique. A single chip with different Cu TSV diameters (3, 5, and 8 µm), all having the same depth and processing conditions was studied. Prior to the measurements, the chip was annealed at 420 °C (30 min), leading to microstructurally stable Cu TSVs. The mean measured hydrostatic stresses were (190 ± 25) MPa (3 µm diameter), (138 ± 19) MPa (5 µm diameter), and (209 ± 26) MPa (8 µm diameter), respectively. No clear relationship between the measured stress and Cu TSV diameter was observed. This trend is attributed to the operation of stress relaxation mechanisms in the polycrystalline Cu TSVs, which includes plastic deformation, grain boundary sliding, void formation/growth, and rate-controlled dislocation motion, which are often neglected in reported finite element analysis studies. Additionally, this study highlights that the thermo-mechanical behavior of Cu TSVs is significantly influenced by their thermal history.

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Notes

  1. Certain commercial equipment, instruments, or materials are identified in this paper to specify experimental or theoretical procedures. Such identification does not imply recommendation by NIST nor the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.

References

  1. Okoro C, Eneman G, Gonzalez M, Vandevelde B, Swinnen B, Stoukatch S, Beyne E, Vandepitte D (2007) Analysis of the induced stresses in silicon during thermocompression Cu-Cu bonding of Cu-through-vias in 3D-SIC architecture. In: 57th Proceedings of electronics components and technology conference (ECTC), June 2007, Reno, USA pp 249–255

  2. International Technical Roadmap for Semiconductors (ITRS) (2013) Edition on interconnects, http://www.itrs.net/links/2013ITRS/2013Chapters/2013Interconnect.pdf

  3. Okoro C, Levine LE, Xu R, Hummler K, Obeng YS (2014) Synchrotron-based measurement of the impact of thermal cycling on the evolution of stresses in Cu through-silicon vias. J Appl Phys 115:243509

    Article  Google Scholar 

  4. Okoro C, Levine LE, Xu R, Hummler K, Obeng YS (2014) Non-destructive measurement of the residual stresses in copper through-silicon vias using synchrotron-based micro-beam X-ray diffraction. IEEE Trans Electron Devices 61:2473–2479

    Article  Google Scholar 

  5. Levine LE, Okoro C, Xu R (in preparation) Full elastic strain and stress tensor measurements from individual dislocation cells in copper through-Si vias

  6. Liu X, Thadesar PA, Taylor CL, Kunz M, Tamura N, Bakir MS, Sitaraman SK (2013) Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron X-ray diffraction. J Appl Phys 114:064908

    Article  Google Scholar 

  7. Budiman AS, Shin H-A-S, Kim B-J, Hwang S-H, Son H-Y, Suh M-S, Chung Q-H, Byun K-Y, Tamura N, Kunz M, Joo Y-C (2012) Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits. Microelectron Reliab 52:530–533

    Article  Google Scholar 

  8. Shin H, Kim B, Kim J, Hwang S, Budiman A, Son H, Byun K, Tamura N, Kunz M, Kim D, Joo Y (2012) Microstructure evolution and defect formation in Cu through-silicon vias (TSVs) during thermal annealing. J Electron Mater 41:712–719

    Article  Google Scholar 

  9. Liu X, Thadesar PA, Taylor CL, Kunz M, Tamura N, Bakir MS, Sitaraman SK (2013) Thermomechanical strain measurement by synchrotron X-ray diffraction and data interpretation for through-silicon vias. Appl Phys Lett 103:022107

    Article  Google Scholar 

  10. Murray CE, Graves-Abe T, Robison R, Cai Z (2013) Sub micron mapping of strain distributions induced by three-dimensional through-silicon via features. Appl Phys Lett 102:251910

    Article  Google Scholar 

  11. Sanchez DF, Laloum D, Weleguela MLD, Ulrich O, Audoit G, Grenier A, Micha J-S, Robach O, Lorut F, Gergaud P, Bleuet P (2014) X-ray µ-laue diffraction analysis of Cu through-silicon vias: a two-dimensional and three-dimensional study. J Appl Phys 116:163509

    Article  Google Scholar 

  12. Budiman AS, Shin H, Kim B-J, Hwang S-H, Son H-Y, Suh M-S, Chung Q-H, Byun K-Y, Joo Y-C, Caramto R, Smith L, Kunz M, Tamura N (2012) Comparison of mechanical stresses of Cu through-silicon via (TSV) samples fabricated by hyinx vs. SEMATECH using synchrotron X-ray microdiffraction for 3-D integration and reliability. In: International interconnect technology conference (IITC), May 2012, San Jose, CA, USA

  13. Zhang C, Li L (2011) Characterization and design of through-silicon via arrays in three-dimensional ICs based on thermomechanical modeling. IEEE Trans Electron Devices 58:279–287

    Article  Google Scholar 

  14. Selvanayagam CS, Lau JH, Zhang X, Seah SKW, Vaidyanathan K, Chai TC (2008) Nonlinear thermal stress/strain analyses of copper filled TSV (Through Silicon Via) and their flip-chip microbumps. In: Electronic components and technology conference (ECTC), May 2008, Lake Buena Vista, FL, USA pp 1073–1081

  15. Ryu S-K, Lu K-H, Jiang T, Im J-H, Huang R, Ho PS (2012) Effect of thermal stresses on carrier mobility and keep-out zone around through-silicon vias for 3-D integration. IEEE Trans Device Mater Reliab 12:255–262

    Article  Google Scholar 

  16. Karmarkar A (2009) “Performance and reliability Analysis of 3D-Integration Structures Employing Through Silicon Via (TSV)”, International Reliability Physics Symposium (IRPS). Canada, April, Montreal, pp 682–687

    Google Scholar 

  17. Che FX, Putra WN, Heryanto A, Trigg A, Gan CL (2013) Study on Cu Protrusion of Through-Silicon Via. IEEE Trans Compon Packag Manuf Technol 3:732–739

    Article  Google Scholar 

  18. Rosenberg R, Edelstein DC, Hu C-K, Rodbell KP (2000) Copper metallization for high performance silicon technology. Ann Rev Mater Sci 30:229–262

    Article  Google Scholar 

  19. Okoro C (2010) Thermo-mechanical characterization of copper through-silicon via interconnect for 3D chip stacking. PhD Thesis, Katholieke Universiteit Leuven, Belgium (Dec. 2010)

  20. Okoro C, Huyghebaert C, van Olmen J, Labie R, Vandevelde B, Beyne E, Vandepitte D (2010) Elimination of the axial deformation problem of Cu-TSV in 3D integration. In: Stress-induced phenomena in metallization: 11th international workshop, Dresden, Germany, Applied Institute of Physics (AIP) Conferences Proceedings Nov. 2010, vol 1300, pp 214–220

  21. Huyghbaert C, van Olmen J, Okoro C, Coenen J, Jourdain A, van Cauwenberghe M, Agarwal R, Phommahaxay A, Stucchi M, Soussan P (2010) Enabling 10 µm pitch hybrid Cu-Cu IC stacking with through silicon vias. In: 60th Proceedings, electronics components and technology conference (ECTC), June 2010, Las Vegas, USA pp 1083–1087

  22. De Messemaeker J, Pedreira OV, Philipsen H, Beyne E, De Wolf I, Van der Donck T, Croes K (2013) Impact of post-plating anneal and through-silicon via dimensions on Cu pumping. In: 64th Proceedings, electronics components and technology conference (ECTC), May 2013, Las Vegas, NV

  23. Levine LE, Geantil P, Larson BC, Tischler JZ, Kassner ME, Liu W, Stoudt MR, Tavazza F (2011) Disordered long-range internal stresses in deformed copper and the mechanisms underlying plastic deformation. Acta Mater 59:5803–5811

  24. Larson BC, Yang W, Ice GE, Budai JD, Tischler JZ (2002) Three-dimensional X-ray structural microscopy with submicrometre resolution. Nature 415:887–890

    Article  Google Scholar 

  25. Marro J, Okoro C, Obeng Y, Richardson K (2014) Defect and microstructural evolution in thermally cycled Cu through-silicon vias. Microelectron Reliab 54:2586–2593

    Article  Google Scholar 

  26. Okoro C, Vanstreels K, Labie R, Lühn O, Vandevelde B, Verlinden B, Vandepitte D (2010) Influence of annealing conditions on the mechanical and microstructural behavior of electroplated Cu-TSV. J Micromech Microeng 20:045032

    Article  Google Scholar 

  27. Okoro C, Golshany F, Lau JW, Hummler K, Obeng YS (2014) A detailed failure analysis examination of the effect of thermal cycling on Cu TSV reliability. IEEE Trans Electron Devices 61(1):15–22

    Article  Google Scholar 

  28. Heryanto A, Putra WN, Trigg A, Gao S, Kwon WS, Che FX, Ang XF, Wei J, Made RI, Gan CL, Pey KL (2012) Effect of copper TSV annealing on via protrusion for TSV wafer fabrication. J Electron Mater 41:2533–2542

    Article  Google Scholar 

  29. De Wolf I, Croes K, Pedreira OV, Labie R, Redolfi A, Van De Peer M, Vanstreels K, Okoro C, Vandevelde B, Beyne E (2011) Cu pumping in TSVs: effect of Pre-CMP thermal budget. Microelectron Reliab 51:1856–1859

    Article  Google Scholar 

  30. Chaudhari P (1974) Hillock growth in thin films. J Appl Phys 45:4339–4346

    Article  Google Scholar 

  31. Gladkikh A, Lereah Y, Glickman E, Karpovski M, Palevski A, Schubert J (1995) Hillock formation during electromigration in Cu and Al thin films: three-dimensional grain growth. Appl Phys Lett 66:1214

    Article  Google Scholar 

  32. Kong LW, Lloyd JR, Yeap KB, Zschech E, Rudack A, Liehr M, Diebold A (2011) Applying X-ray microscopy and finite element modeling to identify the mechanism of stress-assisted void growth in through-silicon vias. J Appl Phys 110:053502

    Article  Google Scholar 

  33. Shaw TM et al (2002) Stress voiding in wide copper lines. In: Baker SP et al (eds) 6th workshop on stress-induced phenomena in metallization, AIP Conferences Proceedings vol 612, pp 177–183

  34. Gleiter H, Chalmers B (1972) High angle grain boundaries. In: Chalmers B, Christian JW, Massalski TB (eds) Progress in materials science, vol 16. Pergamon Press, Oxford, pp 1–272

    Google Scholar 

  35. Ballo P, Slugen V (2005) Grain boundary sliding and migration in copper: the effect of vacancies. Comput Mater Sci 33:491–498

    Article  Google Scholar 

  36. Intrater J, Machlin ES (1959) Grain boundary sliding and intercrystalline cracking. Acta Metall 7:140–143

    Article  Google Scholar 

  37. Qi Y, Krajewski PE (2007) Molecular dynamics simulations of grain boundary sliding: the effect of stress and boundary misorientation. Acta Mater 55:1555–1563

    Article  Google Scholar 

  38. Shiga M et al (2004) Stress-assisted grain boundary sliding and migration at finite temperature: a molecular dynamics study. Phys Rev B 70:054102

    Article  Google Scholar 

  39. Shi J, Zikry MA (2009) Grain size, grain boundary sliding, and grain boundary interaction effects on nanocrystalline behavior. Mater Sci Eng A 520:121–133

    Article  Google Scholar 

  40. Cherman VO, De Messemaeker J, Croes K, Dimcic B, Van der Plas G, De Wolf I, Beyer G, Swinnen B (2012) Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage. In: IEEE international reliability physics symposium (IRPS), April 2012, Anaheim, CA pp 2B.3.1–2B.3.5

  41. Vinci RP, Zielinski EM, Bravman JC (1995) Thermal strain and stress in copper thin films. Thin Solid Films 262:142–153

    Article  Google Scholar 

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Acknowledgements

This research used resources of the Advanced Photon Source, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. This work was supported in part by the National Institute of Standards and Technology (NIST) under Grant 70NANB15H021. The authors will also like to thank SEMATECH, and Dr. Klaus Hummler for samples used in this work and Mr. Joon-Jung Ahn of NIST, for assistance with the AFM tool.

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Correspondence to Chukwudi Okoro.

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Okoro, C., Levine, L.E., Xu, R. et al. Experimental measurement of the effect of copper through-silicon via diameter on stress buildup using synchrotron-based X-ray source. J Mater Sci 50, 6236–6244 (2015). https://doi.org/10.1007/s10853-015-9184-9

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