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DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip

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Abstract

In wireless on-chip network, the reliability of data packet transmission in the link faces great challenges due to crosstalk between lines, noise and transient faults, which seriously affects the overall performance of the network. Therefore, fault tolerance becomes critical in link design. In addition, the traditional fault-tolerant solution based on the error recovery strategy brings a lot of retransmission overhead under high failure rate. Hence, in this paper we propose a new fault-tolerant scheme based on DVFS error avoidance strategy, which dynamically adjusts the voltage and frequency in the network based on the real-time status of the network, thereby reducing the occurrence of faults. Experiments indicate that compared with the traditional fault-tolerant scheme based on error recovery strategy, this paper achieves a huge performance improvement with less power consumption and area overhead.

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References

  1. Agyeman MO, Vien QT, Ahmadinia A, Yakovlev A, Tong KF, Mak T (2017) A resilient 2-D waveguide communication fabric for hybrid wired-wireless NoC design. IEEE Transactions on Parallel & Distributed Systems 28(2):359–373

  2. Bogdan P (2015) Mathematical modeling and control of multifractal workloads for data-center-on-a-chip optimization. In: Proceedings of the 9th international symposium on networks-on-Chip, September 28-30 Vancouver, BC, Canada

  3. Burd T, Brodersen R (2000) Design issues for dynamic voltage scaling. In: Proc. international symposium on low power electronics and design, pp 9–14

  4. Catania V, Mineo A, Monteleone S, Palesi M, Patti D (2015) Noxim: an open, extensible and cycle-accurate network on chip simulator. In: Proc. IEEE 26th international conference on application-specific systems (ASAP), pp 162-163

  5. Constantinescu C (2003) Trends and challenges in VLSI circuit reliability. IEEE Micro 23(4):14–19

    Article  Google Scholar 

  6. Fang Z, Wu N, Yunfei Y, Fen G (2014) NoC voltage frequency islands partition method with multi-constraints. Journal of Southeast University 44(6):1131–1137

  7. Intel XScale microarchitecture. http://developer.intel.com/design/intelxscale/

  8. Jha NK (2001) Low power system scheduling and synthesis. In: Proc. international conference on computer-aided design, pp 259–263

  9. Kim J, Horowitz M (2002) Adaptive supply serial links with sub-1V operation and per-pin clock recovery. In: Proc. international solid-state circuits conference

  10. Kim J, Horowitz MA (2002) Adaptive supply serial links with sub-1-V operation and per-pin clock recovery. IEEE J Solid State Circuits 37(11):1403–1413

    Article  Google Scholar 

  11. Mineo A, Rusli MS, Palesi M, Ascia G, Catania V, Marsono MN (2015) A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures. In: Proc. Design, automation & test in Europe conference & exhibition (DATE), pp 513-518

  12. Mineo A, Palesi M, Ascia G, Catania V (2016) Runtime tunable transmitting power technique in mm-wave WiNoC architectures. IEEE Transactions on Very Large Scale Integration Systems 24(4):1535–1545

    Article  Google Scholar 

  13. Murali S, Theocharides T, Vijaykrishnan N, Irwin MJ, Benini L, De Micheli G (2005) Analysis of error recovery schemes for networks on chips. IEEE Design & Test of Computers 22(5):434–442

  14. Schley G, Batzolis N, Radetzki M (2013) Fault localizing end-to-end flow control protocol for networks-on-chip [C]. In: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP'13) pp 454-461

  15. Shang L, Peh LS, Jha NK (2003) Dynamic voltage scaling with links for power optimization of interconnection networks. In: Proc. International symposium on high-performance computer architecture (HPCA'03) pp 91-102

  16. Sridhara SR, Shanbhag NR (2004) Coding for systern-on-chip networks: a unified framework. In: Proc. 41st Design automation conference, pp 103-106

  17. Transmeta Crusoe microarchitecture. http://www.transmeta.com

  18. Vonbun M, Wild T, Herkersdorf A (2016) Estimation of end-to-end packet error rates for NoC multicasts. In: Proc. International conference on architecture of computing systems. (ARCS'16) pp 363-374

  19. Ouyang Y, Hu L, An X, Li J, Liang, H (2018) High performance EMS fault tolerant scheme for wireless network on chip [J]. Yi Qi Yi Biao Xue Bao/Chinese Journal of Scientific Instrument. 39. 132-140.https://doi.org/10.19650/j.cnki.cjsi.J1703037

  20. Zhang M, Shanbhag NR (2006) A soft error rate analysis (SERA) methodology. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(10):2140–2155

    Article  Google Scholar 

  21. Zimmer H, Jantsch A (2003) A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. In: Proc. First IEEE/ACM/IFIP international conference on hardware/software codesign & system synthesis, pp 188-193

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Acknowledgment

We would like to thank the anonymous reviewers for their tremendous feedback as well as members of our research group for their thoughts and comments on this work. This work is sponsored by National Nature Science Foundation of China (NO.61874157, NO.61674048, NO.61874156), Anhui Province Nature Science Foundation (KJ20180A0783).

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Authors and Affiliations

  1. School of Computer and Information, Hefei University of Technology, Hefei, China

    Yiming Ouyang & Lizhu Hu

  2. School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei, China

    Qi Wang & Huaguo Liang

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  1. Yiming Ouyang
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  2. Qi Wang
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  3. Lizhu Hu
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  4. Huaguo Liang
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Correspondence to Qi Wang.

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Ouyang, Y., Wang, Q., Hu, L. et al. DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip. J Electron Test 35, 767–777 (2019). https://doi.org/10.1007/s10836-019-05841-9

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  • DOI: https://doi.org/10.1007/s10836-019-05841-9

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