Abstract
With increasing scale of Field Programmable Gate Arrays (FPGAs), architecture of interconnect resources (IRs) in FPGA is becoming more and more complicated. IR testing plays an important role to guarantee correct functionality of FPGAs. Usually, architecture of Global IRs is regular, while architecture of Local IRs is more complicated compared to Global IRs. In the paper, a generic IR model revealing the connection relationships for both Global and Local IRs in Xilinx series FPGAs is studied. A routability-aware algorithm based on the generic IR model is also presented. Test configurations (TCs) can be automatically generated by the proposed algorithm. Thus, both Global and Local IRs can be tested with identical method. Further, the algorithm is generic and independent of type and size of FPGAs. The algorithm is evaluated in Virtex series FPGAs. Experimental results demonstrate that the routing algorithm is applicable to Virtex series FPGAs with higher IR coverage achieved.
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This work was supported in part by the Shenzhen Development and Reform Commission under Grant JSGG20150511104613104.
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Appendix
Appendix
BIST: built-in self-test
CLB: configurable logic block
DFF: D flip-flop
FPGA: field programmable gate array
IOB: input/output blocks
IR: interconnect resource
NDP: node disjoint path
PIP: programmable-interconnect-point
PUT: path under test
SM: switch matrix
TC: test configuration
TR: test responses
TV: test vector
WUT: wire segments-under-test
XDL: Xilinx design language
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Ruan, A., Huang, H., Wang, J. et al. A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs. J Electron Test 32, 749–762 (2016). https://doi.org/10.1007/s10836-016-5622-0
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DOI: https://doi.org/10.1007/s10836-016-5622-0