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Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT

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Abstract

This paper presents a method for operational testing of a memristor-based look-up table (LUT) memory block. In the proposed method the deterioration of the memristors (as storage elements of a LUT), is modeled based on the reduction of the resistance range, a phenomenon well known as reported in the technical literature. A quiescent current technique is used to diagnose the memristors when deterioration results in a change of state, thus leading to a fault. In addition to testing, the proposed method can be utilized also for continuous monitoring of the memristor deterioration in the LUT. The deterioration of the memristors is modeled using a simple yet accurate equivalent circuit. The proposed method is simulated using LTSPICE and extensive simulation results are presented for operational deterioration with respect to different features such as LUT dimension, range of memristance and MOSFET feature size. These results show that the proposed test method is highly efficient for testing and monitoring a LUT in the presence of deteriorating multiple memristors.

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Authors and Affiliations

  1. Faculty of Engineering, The University of Nottingham, Malaysia, Semenyih, Malaysia

    T. Nandha Kumar & Haider A. F. Almurib

  2. Department of ECE, Northeastern University, Boston, MA, 02115, USA

    Fabrizio Lombardi

Authors
  1. T. Nandha Kumar
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  2. Haider A. F. Almurib
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  3. Fabrizio Lombardi
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Corresponding author

Correspondence to T. Nandha Kumar.

Additional information

Responsible Editor: S. Hamdioui

This manuscript is an extended version of [10] by the same authors

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Kumar, T.N., Almurib, H.A.F. & Lombardi, F. Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT. J Electron Test 32, 587–599 (2016). https://doi.org/10.1007/s10836-016-5611-3

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  • DOI: https://doi.org/10.1007/s10836-016-5611-3

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