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Contactless Testing of Circuit Interconnects

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Abstract

State-of-the-art printed circuit boards (PCBs) have become extremely dense and are not fully accessible for applying physical testing solutions. Extra steps are required in the design and manufacturing process for testing advanced printed wiring boards (PWBs) with embedded passive components. This processing is further complicated by upcoming sequential build-up (SBU) technologies that provide feature sizes smaller than 10 μm and that do not allow physical access for testing the interconnect between two pads. In this paper, we propose a new contactless technique for overcoming the SBU challenge for testing interconnects between embedded components. A test trace is employed as a sensor, which senses the terminations of the trace being tested. The simulation and analysis results of this study demonstrate the feasibility of this concept for application to SBU and conventional PCB/PWB interconnect testing to overcome the barriers to physical access. Robustness of the approach has been studied against packaging deviations and possible testing process variations. To ensure defect detection with feasible margins, design for testability (DfT) rules have been established for practical PCB dimensions.

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Authors and Affiliations

  1. Dept of Computer Science, Electrical, & Space Engineering, Luleå University of Technology, Luleå, Sweden

    Abdelghani Renbi & Jerker Delsing

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  1. Abdelghani Renbi
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  2. Jerker Delsing
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Correspondence to Abdelghani Renbi.

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Responsible Editor: H. Manhaeve

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Renbi, A., Delsing, J. Contactless Testing of Circuit Interconnects. J Electron Test 31, 229–253 (2015). https://doi.org/10.1007/s10836-015-5524-6

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  • DOI: https://doi.org/10.1007/s10836-015-5524-6

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