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Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors

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Abstract

There is an increasing concern to reduce the cost and overheads during the development of reliable systems. Selective protection of most critical parts of the systems represents a viable solution to obtain a high level of reliability at a fraction of the cost. In particular to design a selective fault mitigation strategy for processor-based systems, it is mandatory to identify and prioritize the most vulnerable registers in the register file as best candidates to be protected (hardened). This paper presents an application-based metric to estimate the criticality of each register from the microprocessor register file in microprocessor-based systems. The proposed metric relies on the combination of three different criteria based on common features of executed applications. The applicability and accuracy of our proposal have been evaluated in a set of applications running in different microprocessors. Results show a significant improvement in accuracy compared to previous approaches and regardless of the underlying architecture.

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References

  1. Azambuja JR, Pagliarini S, Rosa L, Lima Kastensmidt F (2011) Exploring the limitations of software-based techniques in SEE fault coverage. J Electron Test 27(4):541–550

    Article  Google Scholar 

  2. Benso A, Chiusano S, Prinetto P, Tagliaferri L (2000) A C/C++ source to source compiler for dependable applications, in Proc. IEEE Int. Conf. on Dependable Systems and Networks (DSN), pp. 71–78

  3. Bergaoui S, Vanhauwaert P, Leveugle R (2010) A new critical variable analysis in processor-based systems. IEEE Trans Nucl Sci 57(4):1992–1999

    Article  Google Scholar 

  4. Chapman K (2003) PicoBlaze KCPSM3. 8-bit Micro Controller for Spartan-3, Virtex-II and Virtex-II, Xilinx Ltd

  5. Chielle E, Azambuja JR, Barth RS, Almeida F, Lima Kastensmidt F (2013) Evaluating selective redundancy in data-flow software-based techniques. IEEE Trans Nucl Sci 60(4):2768–2775

    Article  Google Scholar 

  6. Cuenca-Asensi S, Martínez-Álvarez A, Restrepo-Calle F, Palomo FR, Guzmán-Miranda H, Aguirre MA (2011) A novel co-design approach for soft errors mitigation in embedded systems. IEEE Trans Nucl Sci 58(3):1059–1065

    Article  Google Scholar 

  7. Giacinto P, Wang N, Kalbarczyk Z, Patel S, Iyer R (2005) An experimental study of soft error in microprocessors. IEEE MICRO 25(6):30–39

    Article  Google Scholar 

  8. Goloubeva O, Rebaudengo M, Reorda MS, Violante M (2006) Software-Implemented Hardware Fault Tolerance (Vol. XIV). Springer

  9. Hamdioui S, Nicolaidis M, Gizopoulos D, Grasset A, Guido G, Bonnot P (2013) Reliability challenges of real-time systems in forthcoming technology nodes. Proc. Design, Automation and Test in Europe (DATE '13), EDA Consortium, Pp. 129–134

  10. L. M. O. S. S. (2010) Hangout and S. Jan, TheMinimips Project [Online]. Availiable: http://www.opencores.org/projects.cgi/ web/minimips/overview 2010

  11. Lee J, Shrivastava A (2011) Static analysis of register file vulnerability. IEEE Trans Comput-Aided Design Integr Circuits Syst 30(4):607–616

    Article  Google Scholar 

  12. Lindoso A, Entrena L, San Millan E, Cuenca-Asensi S, Martínez-Álvarez A, Restrepo-Calle F (2012) A co-design approach for SET mitigation in embedded systems. IEEE Trans Nucl Sci 59(4):1034–1039

    Article  Google Scholar 

  13. Martínez-Álvarez A, Cuenca-Asensi S, Restrepo-Calle F, Palomo Pinto FR, Guzmán-Miranda H, Aguirre MA (2012) Compiler-directed soft error mitigation for embedded systems. IEEE Trans Dependable Secure Computing 9(2):159–172

    Article  Google Scholar 

  14. Martínez-Álvarez A, Restrepo-Calle F, Vivas Tejuelo LA, Cuenca-Asensi S (2013) Fault tolerant embedded systems design by multi-objective optimization. Expert Systems Appl 40(17):6813–6822

  15. Mentor Graphics (2014) http://www.model.com/content/modelsim-support

  16. Mukherjee SS, Weaver C, Emer J, Reinhardt SK, Austin T (2003) A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, in Proc. 36th Int. Symp. on Microarchitecture., MICRO-36. pp. 29–40

  17. Nicolaidis M (2005) Design for soft error mitigation. IEEE Trans Device Mater Rel 5(3):405–418

  18. Nicolaidis M (2011) Soft Errors in Modern Electronic Systems. 1st Ed. Frontiers in Electronic Testing Series, vol. 41. Springer

  19. Nicolescu B, Savaria Y, Velazco R (2004) Software detection mechanisms providing full coverage against single bit-flip faults. IEEE Trans NuclSci 51(6):3510–3518

    Google Scholar 

  20. Oh N, Shirvani PP, McCluskey EJ (2002) Control-flow checking by software signatures. IEEE Trans Rel 51(1):111–122

    Article  Google Scholar 

  21. Pattabiraman K, Kalbarczyk Z, Iyer RK (2005) Application-based metrics for strategic placement of detectors,“ in Proc. 11th Pacific Rim Int. Symp. on Dependable Computing, pp.8, 12–14

  22. Portela-Garcia M, Lindoso A, Entrena L, Garcia-Valderas M, Lopez-Ongil C, Marroni N, Pianta B, Bolzani Poehls L, Vargas F (2012) Evaluating the effectiveness of a software-based technique under SEEs using FPGA-based fault injection approach. J Electron Test 28(6):777–789

    Google Scholar 

  23. Pratt B, Caffrey M, Carroll JF, Graham P, Morgan K, Wirthlin M (2008) Fine-grain SEU mitigation for FPGAs using partial TMR. IEEE Trans Nucl Sci 55(4):2274–2280

    Article  Google Scholar 

  24. Rehman S, Shafique M, Kriebel F, Henkel J (2011) Reliable software for unreliable hardware: embedded code generation aiming at reliability, In Proc.7th IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES + ISSS '11), pp. 237–246

  25. Restrepo-Calle F, Martínez-Álvarez A, Cuenca-Asensi S, Jimeno A (2013) Selective SWIFT-R: a flexible software-based technique for soft error mitigation in low-cost embedded systems. J Electron Test 29(6):825–838

    Article  Google Scholar 

  26. Ruano O, Maestro JA, Reviriego P (2009) A methodology for automatic insertion of selective TMR in digital circuits affected by SEUs. IEEE Trans Nucl Sci 56(4):2091–2102

    Article  Google Scholar 

  27. Sridharan V, Kaeli DR (2008) Quantifying Software Vulnerability, in Proc. Workshop Radiation Effects and Fault Tolerance in Nanometer Tech. WREFT, pp. 323–328

  28. Vargas F, Rocha CA, Farina A, de Alecrim AA Jr (2007) Embedded signature monitoring based on profiling deployed software technique. IEEE Int East–west Des Test Symp, Yerevan, Armenia, pp. 230–236

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Acknowledgments

This work was funded in part by the Spanish Ministry of Education, Culture and Sports with the project “Developing hybrid fault tolerance techniques for embedded microprocessors” (PHB2012-0158-PC).

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Correspondence to Felipe Restrepo-Calle.

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Responsible Editor: L. M. Bolzani Pöhls

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Restrepo-Calle, F., Cuenca-Asensi, S., Martínez-Álvarez, A. et al. Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors. J Electron Test 31, 139–150 (2015). https://doi.org/10.1007/s10836-015-5513-9

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  • DOI: https://doi.org/10.1007/s10836-015-5513-9

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