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Pseudo Functional Path Delay Test through Embedded Memories

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Abstract

Memory arrays cannot be as easily tested as other storage elements. They can be considered as non-scan cells. Memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these methods do not focus on the interaction between memory and surrounding logic, so may not cover timing critical paths. In this paper, we propose path delay test through memory arrays using pseudo functional test with K Longest Paths Per Gate (PKLPG). Long paths captured into a non-scan cell (including a memory cell) are propagated to a scan cell or primary output, and non-scan cells are initialized so that they can launch transitions onto long paths. This allows scan tests to cover critical paths into and out of memory arrays.

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References

  1. Abadir MS, Reghbati HK (1983) Functional testing of semiconductor random access memories. ACM Comput Sur (CSUR) 15(3):175–198

    Article  Google Scholar 

  2. Banga M, Rahagude N, Hsiao MS (2011) “Design-for-test methodology for non-scan at-speed testing,” Proc Design Automation Test in Europe Conference Exhibition (DATE), pp. 1–6

  3. Belete D, Razdan A, Schwarz W, Raina R, Hawkins C, Morehead J (2002) “Use of DFT techniques in speed grading a 1 GHz + microprocessor,” Proc IEEE International Test Conference pp. 1111–1119

  4. Bian K, Walker DMH, Khatri SP, Lahiri S (2013) “Mixed structuralfunctional path delay test generation and compaction,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) pp. 7–12

  5. Crouch AL, McKeown JL, Shepard CG (1999) “Multiple BIST controllers for testing multiple embedded memory arrays,” US Patent 5,995,731

  6. Nadeau-Dostie B, Takeshita K, Cote JF (2008) “Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks,” IEEE International Test Conference, pp. 1–10

  7. Pant P, Zelman J (2009) “Understanding Power Supply Droop during At- Speed Scan Testing,” 27th IEEE VLSI Test Conference, pp. 227–232

  8. Qiu W, Wang LC, Walker DMH, Reddy D, Xiang L, Li Z, Shi W, Balachandran H (2004) “K longest paths per gate (KLPG) test generation for scan-based sequential circuits,” Proc IEEE International Test Conference, pp. 223–231

  9. Rajsuman R (2001) Design and test of large embedded memories: An overview. IEEE Des Test Comput 18(3):16–27

    Article  Google Scholar 

  10. Ross DE, Wood T, Giles G (2000) “Conversion of small functional test sets of nonscan blocks to scan patterns,” Proc IEEE International Test Conferenc, pp. 691–700

  11. Seok G, Hong K, Mohammad B (2012) “Write-through method for embeddedmemory with compression Scan-based testing, ” Proc 30th IEEE VLSI Test Sympositum pp. 158–163

  12. Tuna M, Benabdenbi M, Greiner A (2007) “At-Speed Testing of Core- Based System-on-Chip Using an Embedded Micro-Tester,” 25th IEEE VLSI Test Symposium pp, 447–454

  13. Yang F and Chakravarty S (2010) “Testing of latch based embedded arrays using scan tests,” Proc IEEE International Test Conference pp, 1–10

  14. Zarrineh K, Upadhyaya SJ, Chakravarty S (1998) “A new framework for generating optimal march tests for memory arrays,” IEEE Internatonal Test Conference pp, 73–82

  15. Zarrineh K and Upadhyaya SJ (1999) “On programmable memory builtin self test architectures,” Proc Design Automation and Test in Europe Conference and Exhibition, pp. 708–713

  16. Zeng J, Abadir M, Vandling G, Wang L, Kolhatkar A, Abraham J (2004) “On correlating structural tests with functional tests for speed binning of high performance design,” Proc IEEE International Test Conference pp. 31–37

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Acknowledgments

This work was supported in part by the Semiconductor Research Corporation under contract 2010-TJ-2096 and by the National Science Foundation under grant CCF-1117982. Punj Pokharel performed this work while a student at the Texas A&M University.

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Authors and Affiliations

  1. Department Computer Science and Engineering, Texas A&M University, College Station, TX, USA

    Yukun Gao, Tengteng Zhang, Swati Chakraborty & D. M. H. Walker

  2. NVIDIA Corp, 2701 San Tomas Expressway, Santa Clara, CA, USA

    Punj Pokharel

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  1. Yukun Gao
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  2. Tengteng Zhang
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  3. Punj Pokharel
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  4. Swati Chakraborty
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  5. D. M. H. Walker
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Correspondence to Yukun Gao.

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Responsible Editor: Th. Haniotakis

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Gao, Y., Zhang, T., Pokharel, P. et al. Pseudo Functional Path Delay Test through Embedded Memories. J Electron Test 31, 35–42 (2015). https://doi.org/10.1007/s10836-014-5497-x

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  • DOI: https://doi.org/10.1007/s10836-014-5497-x

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