Abstract
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because fault-tolerant hardwares help to mask the effects caused by increased levels of defects, testing the functionality of the chip together with the embedded fault-tolerance becomes a tremendous challenge. In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered. In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and it can generate a set of vectors that can test the TMR-based nano circuit as a single entity. Experimental results reported for ISCAS’85 and ITC99 circuits demonstrate that the bilateral testing can help to capture many more defects which the single stuck-at fault misses.
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Responsible Editor: N. A. Touba
Supported in part by NSF Grants 0196470, 0305881 and 0417340.
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Fang, L., Hsiao, M.S. Bilateral Testing of Nano-scale Fault-Tolerant Circuits. J Electron Test 24, 285–296 (2008). https://doi.org/10.1007/s10836-007-5041-3
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DOI: https://doi.org/10.1007/s10836-007-5041-3