Abstract
This paper presents an analytical investigation of the electrostatic properties of a moderately doped symmetric gate-all-around nanowire MOSFET having InGaAs channel. The model is continuous from depletion to strong inversion regime that circumvents regional approach, thus smoothly capturing the transition of the charge profile in all regions of operation. The evolution of the model is facilitated by the solution of quasi 2-D Poisson equation with appropriate boundary conditions in a square gate-all-around geometry, incorporating fixed oxide charge and interface trap defects. The determination of mobile charge density leads to the capacitance-voltage (CV) characteristics as a function of gate bias. The CV profile is investigated subject to scaling of physical parameters and material properties. Further, a threshold voltage model is presented for a long channel gate-all-around device that utilizes the well-known double derivative method. This model accurately predicts the threshold voltage variation with fin width, oxide thickness and channel doping, highlighting room for further improvement in electrostatics by incorporating high-k dielectric. The excellent match between the model results and TCAD simulation reflects the validity of the proposed model.
Similar content being viewed by others
Data availability
The data that support the findings of this study are available from the corresponding author upon reasonable request.
References
Liu, Y., Ishii, K., Tsutsumi, T., Masahara, M., Suzuki, E.: Ideal rectangular cross-section Si–Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching. IEEE Electron Dev. Lett. 24(7), 484–486 (2003)
Gámiz, F., Roldán, J., Godoy, A., Carceller, J., Cartujo, P.: Double gate silicon on insulator transistors. A Monte Carlo study. Solid-State Electron. 48(6), 937–945 (2004)
Li, Y., Chou, H.M.: A comparative study of electrical characteristic on sub-10-nm double-gate MOSFETs. IEEE Trans. Nanotechnol. 4(5), 645–647 (2005)
Jiménez, D., Iñíguez, B., Suñé, J., Sáenz, J.J.: Analog performance of the nanoscale double-gate metal-oxide-semiconductor field-effect-transistor near the ultimate scaling limits. J. Appl. Phys. 96(9), 5271–5276 (2004)
Lee, C.W., Yun, S.R.N., Yu, C.G., Park, J.T., Colinge, J.P.: Device design guidelines for nano-scale MuGFETs. Solid-State Electron. 51(3), 505–510 (2007)
Colinge, J.P., Gao, M., Romano-Rodriguez, A., Maes, H., Claeys, C.: Silicon-on-insulator ‘gate-all-around device’. Intern. Technol. Digest Electron Dev. 20, 595–598 (1990)
Singh, N., Buddharaju, K.D., Manhas, S., Agarwal, A., Rustagi, S.C., Lo, G., Balasubramanian, N., Kwong, D.L.: Si, SiGe nanowire devices by top-down technology and their applications. IEEE Trans. Electron Dev. 55(11), 3107–3118 (2008)
Del Alamo, J.A.: Nanometre-scale electronics with III–V compound semiconductors. Nature 479(7373), 317–323 (2011)
Xuan, Y., Wu, Y.Q., Shen, T., Yang, T., Ye, P.D.: High performance submicron inversion-type enhancement-mode lnGaAs MOSFETs with ALD Al2O3, HfO2 and HfAlO as gate dielectrics. IEEE Intern. Electron Dev. Meeting 3, 637–640 (2007)
Xuan, Y., Wu, Y.Q., Ye, P.D.: High-performance inversion-type enhancement-mode lnGaAs MOSFET with maximum drain current exceeding 1 A/mm. IEEE Electron Dev. Lett. 29(4), 294–296 (2008)
Gu, J.J., Liu, Y.Q., Wu, Y.Q., Colby, R., Gordon, R.G., Ye, P.D.: First experimental demonstration of gate-all-around III-V MOSFETs by top-down approach. Intern. Electron Dev. Meeting 12, 32–33 (2011)
Gu, J.J., Wu, H., Liu, Y., Neal, A.T., Gordon, R.G., Peide, D.Y.: Size-dependent-transport study of In0.53 Ga0.47 As gate-all-around nanowire MOSFETs: impact of quantum confinement and volume inversion. IEEE Electron Dev. Lett. 33(7), 967–969 (2012)
Khan, S.U.Z., Hossain, M.S., Rahman, F.U., Zaman, R., Hossen, M.O., Khosru, Q.D.M.: Impact of high-\(\kappa \) gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate-all-around nanowire transistor. Intern. J. Numer. Model Electron. Net. Dev. Fields 28(4), 389–403 (2015)
Rahman, F.U., Hossain, M.S., Khan, S.U.Z., Zaman, R., Hossen, M.O., Khosru, Q.D.M.: Characterization of interface trap density of In-rich InGaAs gate-all-around nanowire MOSFETs. Intern. Conf. Electr. Comput. Eng. 3, 674–677 (2012)
Khosru, Q.D.M., Khan, S.U.Z., Datta, K.: Study of electrostatics and transport properties of multigate graded nanowire channel MOSFETs. ECS Trans. 72(4), 325 (2016)
Islam, M., Masud, M., Khosru, Q.D.M.: An accurate physical based transport model of gate-all-around \(\text{ In}_{x}\text{ Ga}_{1-x}\text{ As }\) nanowire MOSFET using Gaussian-like transmission co-efficient. Materials Focus 7(2), 268–272 (2018)
Taur, Y., Liang, X., Wang, W., Lu, H.: A continuous, analytic drain-current model for dg mosfets. IEEE Electron Dev. Lett. 25(2), 107–109 (2004)
Francis, P., Terao, A., Flandre, D., Van de Wiele, F.: Modeling of ultrathin double-gate nMOS/SOI transistors. IEEE Trans. Electron Dev. 41(5), 715–720 (1994)
Moldovan, O., Cerdeira, A., Jiménez, D., Raskin, J.P., Kilchytska, V., Flandre, D., Collaert, N., Iniguez, B.: Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications. Solid-State Electron. 51(5), 655–661 (2007)
Wu, Y., Wang, W., Koybasi, O., Zakharov, D., Stach, E., Nakahara, S., Hwang, J., Ye, P.: 0.8-V supply voltage deep-submicrometer inversion-mode In0.75 Ga0.25 As MOSFET. IEEE Electron Dev. Lett. 30(7), 700–702 (2009)
Tsormpatzoglou, A., Dimitriadis, C.A., Clerc, R., Pananakakis, G., Ghibaudo, G.: Threshold voltage model for short-channel undoped symmetrical double-gate MOSFETs. IEEE Trans. Electron Dev. 55(9), 2512–2516 (2008)
Trevisoli, R.D., Doria, R.T., de Souza, M., Pavanello, M.A.: Threshold voltage in junctionless nanowire transistors. Semicond. Sci. Technol. 26(10), 105009 (2011)
Sallese, J.M., Chevillon, N., Lallement, C., Iniguez, B., Prégaldiny, F.: Charge-based modeling of junctionless double-gate field-effect transistors. IEEE Trans. Electron Dev. 58(8), 2628–2637 (2011)
Ortiz-Conde, A., Sánchez, F.G., Guzmán, M.: Exact analytical solution of channel surface potential as an explicit function of gate voltage in undoped-body mosfets using the Lambert W function and a threshold voltage definition therefrom. Solid-State Electron. 47(11), 2067–2074 (2003)
Hurley, P.K., O’Connor, É., Djara, V., Monaghan, S., Povey, I.M., Long, R.D., Sheehan, B., Lin, J., McIntyre, P.C., Brennan, B., et al.: The characterization and passivation of fixed oxide charges and interface states in the Al2O3 lnGaAs MOS system. IEEE Trans. Dev. Materials Reliab. 13(4), 429–443 (2013)
Paz, B.C., Casse, M., Barraud, S., Reimbold, G., Faynot, O., Ávila-Herrera, F., Cerdeira, A., Pavanello, M.A.: Drain current model for short-channel triple gate junctionless nanowire transistors. Microelectr. Reliab. 63, 1–10 (2016)
Winitzki, S.: Uniform approximations for transcendental functions. Intern. Conf. Comput. Sci. Appl. 3, 780–789 (2003)
Guide, S.D.U., Version, G.: Synopsys Inc. Mountain View, CA, USA (2012)
Zheng, J., Tsai, W., Lin, T., Lee, Y., Chen, C., Hong, M., Kwo, J., Cui, S., Ma, T.: Ga2 O3 Gd2 O3/Si3 N4 dual-layer gate dielectric for lnGaAs enhancement mode metal-oxide-semiconductor field-effect transistor with channel inversion. Appl. Phys. Lett. 91(22), 223502 (2007)
Goel, N., Majhi, P., Tsai, W., Warusawithana, M., Schlom, D., Santos, M., Harris, J., Nishi, Y.: High-indium-content lnGaAs metal-oxide-semiconductor capacitor with amorphous LaAlO3 gate dielectric. Appl. Phys. Lett. 91(9), 093509 (2007)
Rahman, M., Kim, J.G., Kim, D.H., Kim, T.W., et al.: Characterization of Al incorporation into HfO2 dielectric by atomic layer deposition. Micromachines 10(6), 361 (2019)
Wu, Y., Wang, R., Shen, T., Gu, J., Ye, P.: First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching. In: 2009 IEEE International Electron Devices Meeting (IEDM), pp. 1–4. IEEE (2009)
Chin, H.C., Gong, X., Wang, L., Lee, H.K., Shi, L., Yeo, Y.C.: III–V Multiple-gate field-effect transistors with high-mobility ln0.7 Ga0.3 As channel and epi-controlled retrograde-doped fin. IEEE Electron Dev. Lett. 32(2), 146–148 (2010)
Radosavljevic, M., Dewey, G., Fastenau, J., Kavalieros, J., Kotlyar, R., Chu-Kung, B., Liu, W., Lubyshev, D., Metz, M., Millard, K., et al.: Non-planar, multi-gate InGaAs quantum well field effect transistors with high-k gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications. In: 2010 International Electron Devices Meeting, pp. 6–1. IEEE (2010)
Gu, J.J., Wang, X., Wu, H., Shao, J., Neal, A.T., Manfra, M.J., Gordon, R.G., Ye, P.D.: 20–80nm channel length InGaAs gate-all-around nanowire MOSFETs with EOT=1.2 nm and lowest SS=63mV/dec. In: 2012 International Electron Devices Meeting, pp. 27–6. IEEE (2012)
Liu, F., Zhang, L., Zhang, J., He, J., Chan, M.: Effects of body doping on threshold voltage and channel potential of symmetric dg mosfets with continuous solution from accumulation to strong-inversion regions. Semicond. Sci. Technol. 24(8), 085005 (2009)
Shi, X., Wong, M.: Effects of substrate doping on the linearly extrapolated threshold voltage of symmetrical DG MOS devices. IEEE Trans. Electron Dev. 52(7), 1616–1621 (2005)
Acknowledgements
This work has been carried out in the Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology (BUET). The authors gratefully acknowledge the support and facilities provided by BUET.
Funding
Not Applicable.
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
Conflict of interest
The authors declare no conflict of interest.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Appendix: Difference of surface-center potential in terms of Lambert function
Appendix: Difference of surface-center potential in terms of Lambert function
Generally the double derivative of potential can be written using coarse finite difference method [23] resulting into,
Under symmetric operation, \(E|_{x=0}=0\) and using simplifying assumptions leads to,
Substituting (2) into (A.1) we get,
After some mathematical manipulation, the normalized difference of potential can be expressed as,
From (A.5) the following relation also holds,
Rights and permissions
About this article
Cite this article
Rahman, I.K.M.R., Khan, M.I. & Khosru, Q.D.M. Electrostatic characterization and threshold voltage modeling of inversion type InGaAs gate-all-around MOSFET. J Comput Electron 20, 1504–1512 (2021). https://doi.org/10.1007/s10825-021-01716-5
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10825-021-01716-5