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A review on the compact modeling of parasitic capacitance: from basic to advanced FETs

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Abstract

This paper presents a review on the development of parasitic-capacitance modeling for metal–oxide–semiconductor field-effect transistors (MOSFETs), covering models developed for the simple parallel-plate capacitance and the nonplanar and coplanar plate capacitances required for the intrinsic and extrinsic part of such devices. A comparative study of various extrinsic capacitance models with respect to a reference model is used to analyze the benefits of the various approaches. Capacitance models for basic MOSFETs and advance multigate FETs with two-dimensional (2D) and three-dimensional (3D) structures are reviewed. It is found that the elliptical field lines between the gate electrodes and source/drain region are modeled very well, while deviations of \(\pm 2 \%\) in the orthogonal plate capacitance are observed when the gate electrode thickness is varied from 5 to 20 nm .

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Acknowledgements

The authors would like to thank the Department of Electronics and Communication Engineering, IIT Roorkee, for their valuable support in carrying out this research work.

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Authors and Affiliations

  1. Department of ECE, DVR & Dr. HS MIC College of Technology, Kanchikacherla, Andhra Pradesh, India

    Savitesh Madhulika Sharma

  2. Department of Electronics & Communication Engineering, Adama Science and Technology University, Adama, Ethiopia

    Avtar Singh

  3. Department of ECE, IIT, Roorkee, India

    Sudeb Dasgupta & M. V. Kartikeyan

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  1. Savitesh Madhulika Sharma
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  4. M. V. Kartikeyan
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Correspondence to Savitesh Madhulika Sharma.

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Sharma, S.M., Singh, A., Dasgupta, S. et al. A review on the compact modeling of parasitic capacitance: from basic to advanced FETs. J Comput Electron 19, 1116–1125 (2020). https://doi.org/10.1007/s10825-020-01515-4

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