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Optimal design of a 5.5-GHz low-power high-gain CMOS LNA using the flower pollination algorithm

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Abstract

The design of a low-power, high-gain, highly linear complementary metal–oxide–semiconductor (CMOS) cascode low-noise amplifier (LNA) with an inductive source degeneration circuit for use at 5.5 GHz frequency is optimized using a flower pollination algorithm (FPA) as an evolutionary technique. The FPA is applied to optimize the noise figure (NF) while validating all the design constraints, e.g., on the gain, power dissipation, linearity, stability, and input and output matching. Optimal sizing of the MOS transistors present in the LNA circuit is achieved by using the FPA. Moreover, the FPA helps to estimate the optimal values of the other elements in the LNA circuit. The FPA-based optimal design parameters are used to implement the CMOS LNA circuit in CADENCE IC 6.1.6 software at the UMC 180-nm technology node with a supply voltage of 1.8 V. The designed LNA achieves an input third-order intercept point (IIP3) of 1.77 dBm, power dissipation of 4.29 mW, NF of 0.686 dB, and gain of 24.42 dB at 5.5 GHz. The FPA-based optimal design for the CMOS cascode LNA yields remarkably improved results compared with those in previous literature in terms of the gain, noise figure, power dissipation, and area.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, NIT Durgapur, Durgapur, India

    Sumalya Ghosh, R. Kar, D. Mandal & A. K. Mal

  2. School of Electronics Engineering, KIIT University, Bhubaneswar, India

    Bishnu Prasad De

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  1. Sumalya Ghosh
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Ghosh, S., De, B.P., Kar, R. et al. Optimal design of a 5.5-GHz low-power high-gain CMOS LNA using the flower pollination algorithm. J Comput Electron 18, 737–747 (2019). https://doi.org/10.1007/s10825-019-01322-6

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