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Novel design for a memristor-based full adder using a new IMPLY logic approach

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Abstract

This paper presents and evaluates a novel approach based on material implementation to improve the performance of a 1-bit memristor-based full adder. In addition, two new efficient architectures are presented and evaluated for an 8-bit memristor-based full adder, serial memristor-based full adder and parallel-serial memristor-based full adder. Using the proposed approach, the number of required steps to accumulate the sum and carry-out in the proposed serial and parallel-serial 8-bit memristor-based full adder architectures is 168 and 56, respectively. Moreover, the number of required memristors in the proposed serial and parallel-serial memristor-based full adder architectures is 19 and 33, respectively. The evaluation results show that both delay and density are improved in the proposed architectures compared to other memristor-based full adder architectures.

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  1. ACECR Institute of Higher Education, Isfahan Branch, Isfahan, 84175-443, Iran

    Ahmad Karimi & Abdalhossein Rezai

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  1. Ahmad Karimi
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  2. Abdalhossein Rezai
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Correspondence to Ahmad Karimi or Abdalhossein Rezai.

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Karimi, A., Rezai, A. Novel design for a memristor-based full adder using a new IMPLY logic approach. J Comput Electron 17, 1303–1314 (2018). https://doi.org/10.1007/s10825-018-1198-5

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  • DOI: https://doi.org/10.1007/s10825-018-1198-5

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