Skip to main content
SpringerLink
Log in

Simulation-based performance analysis of an ultra-low specific on-resistance trench SOI LDMOS with a floating vertical field plate

  • Published:
Journal of Computational Electronics Aims and scope Submit manuscript

Abstract

An ultra-low specific on-resistance \((R_\mathrm{{on,sp}})\) trench SOI LDMOS with a floating vertical field plate structure (FVFPT SOI) is proposed in this paper. A floating vertical plate (FVFP) is introduced into the filled oxide trench of a conventional trench SOI LDMOS (CT SOI) to improve its electrical performance. We conduct related performance analysis to this device by simulation and investigate the effects of different parameters on its performance. The FVFP causes an assisted depletion effect especially for the trench surface regions. An ultra-low \(R_\mathrm{{on,sp}}\) is therefore obtained in the FVFP device due to higher drift region doping concentration \((N_\mathrm{{d}})\). A breakdown voltage (BV) of 188V and a \(R_\mathrm{{on,sp}}\) of \(0.9 \hbox { m}\Omega \, \hbox { cm}^{2}\) are realized on a 4.8-\({\upmu }\hbox {m}\)-long drift region, a 7.5-\({\upmu }\hbox {m}\)-thick top-silicon layer and a 0.5-\({\upmu }\hbox {m}\)-thick buried oxide (BOX) layer by our simulation. Eventually, the \(R_\mathrm{{on,sp}}\) for the FVFPT SOI can be reduced by more than 60%, while its BV is maintained the same class as the CT SOI, and the figure of merit (FOM) is enhanced by 155%. And a set of optimal parameters, including the structure parameters of plate and the property parameters of device, are obtained.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  1. Hu, S., Luo, J., Jiang, Y.Y., Cheng, K., Chen, Y., Jin, J., et al.: Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer. Solid State Electron. 117, 146–151 (2015)

    Article  Google Scholar 

  2. Kosina, H., Gritsch, M., Grasser, T., Linton, T., Yu, S., Giles, M.D., et al.: An improved energy transport model suitable for simulation of partially depleted SOI MOSFETs. J. Comput. Electron. 1(3), 371–374 (2002)

    Article  Google Scholar 

  3. Chen, Y., Hu, S., Cheng, K., Jiang, Y.Y., Luo, J., Wang, J., et al.: A novel low specific on-resistance double-gate LDMOS with multiple buried p-layers in the drift region based on the silicon-on-insulator substrate. Superlattices Microstruct. 89, 59–67 (2015)

    Article  Google Scholar 

  4. Zhang, Y., Yu, W.U., You, X., Kang, B.: New development of junction termination techniques for power devices. Chin. J. Electron Devices 32(3), 538–546 (2009)

    Google Scholar 

  5. Orouji, A.A., Rahimifar, A., Jozi, M.: A novel double-gate SOI MOSFET to improve the floating body effect by dual SiGe trench. J. Comput. Electron. 15(2), 537–544 (2016)

    Article  Google Scholar 

  6. Fan, J., Zhang, B., Luo, X.R., Li, Z.J.: High-voltage SOI lateral MOSFET with a dual vertical field plate. Chin. Phys. B 22(11), 645–650 (2013)

    Article  Google Scholar 

  7. Wu, L., Zhang, W., Shi, Q., et al.: Trench SOI LDMOS with vertical field plate. Electron. Lett. 50(25), 1982–1984 (2014)

    Article  Google Scholar 

  8. Li, P.C., Luo, X.R., Luo, Y.C., Zhou, K., Shi, X.L., Zhang, Y.H.: An ultra-low specific on-resistance trench LDMOS with a u-shaped gate and accumulation layer. Chin. Phys. B 24(4), 399–404 (2015)

    Google Scholar 

  9. Pu, Q., Yun, J., Temkin, H., Liu, S.: Ion-enrichment and ion-depletion effect of nanochannel structures. Nano Lett. 4(6), 1099–1103 (2004)

    Article  Google Scholar 

  10. User’s Manual, MEDICI: Two-Dimensional Device Simulation Program, TMA MEDICI 4.2, Technology Modeling Associates Inc., Palo Alto (1998)

  11. Zhang, W., Zhang, B., Qiao, M., Wu, L., Mao, K., Li, Z.: A novel vertical field plate lateral device with ultralow specific on-resistance. IEEE Trans. Electron Devices 61(2), 518–524 (2014)

    Article  Google Scholar 

  12. Xiong, W., Cleavelin, C.R., Wise, R., Yu, S.: Full/partial depletion effects in FinFETs. Electron. Lett. 41(8), 504–506 (2005)

    Article  Google Scholar 

  13. Luo, X., Lei, T.F., Wang, Y.G., Yao, G.L., Jiang, Y.H., Zhou, K., et al.: Low on-resistance SOI dual-trench-gate MOSFET. IEEE Trans. Electron Devices 59(2), 504–509 (2012)

  14. Xia, C., Cheng, X., Wang, Z., Xu, D., Cao, D., Zheng, L., et al.: Improvement of SOI trench LDMOS performance with double vertical metal field plate. IEEE Trans. Electron Devices 61(10), 3477–3482 (2014)

  15. Luo, X., Fan, J., Wang, Y., Lei, T., Qiao, M., Zhang, B., et al.: Ultralow specific on-resistance high-voltage SOI lateral MOSFET. IEEE Electron Device Lett. 32(2), 185–187 (2011)

    Article  Google Scholar 

  16. Luo, X., Luo, Y., Fan, Y., et al.: A low specific on-resistance SOI MOSFET with dual gates and a recessed drain. Chin. Phys. B 22(2), 434–438 (2013)

    Google Scholar 

  17. Shi, Y.M., Liu, J.Z., Yao, S.Y., Ding, Y.H., Zhang, W.H., Dai, H.L.: A dual-trench silicon on insulator high voltage device with an L-shaped source field plate. Acta Phys. Sin. 63(23), 237305–237305 (2014)

    Google Scholar 

  18. Chen, X.B., Sin, J.K.O.: Optimization of the specific on-resistance of the COOLMOS TM. IEEE Trans. Electron Devices 48(2), 344–348 (2001)

    Article  Google Scholar 

  19. Ishihara, K., Yung, C.F., Ayon, A.A., Schmidt, M.A.: Inertial sensor technology using DRIE and wafer bonding with connecting capability. J. Microelectromechanical Syst. 8(4), 403–408 (2000)

    Article  Google Scholar 

  20. Jung, K.B., Song, W.J., Lim, H.W., Lee, C.S.: Parameter study for silicon grass formation in Bosch process. J. Vac.Sci. Technol. B Microelectron. Nanometer Struct. 28(1), 143–148 (2010)

    Google Scholar 

  21. Zhou, K., Luo, X., Li, Z., Zhang, B.: Analytical model and new structure of the variable-k dielectric trench LDMOS with improved breakdown voltage and specific on-resistance. IEEE Trans. Electron Devices 62(10), 3334–3340 (2015)

    Article  Google Scholar 

  22. Wang, A., Bloking, J., Wang, L., Vellaikal, M., Jin, H.J., Lee, Y.S., et al.: Extending HDP for STI fill to 45nm with IPM. In: International Symposium on Semiconductor Manufacturing IEEE, 1–5 (2007)

  23. Barnett, R.: Developments in Si and SiO2 etching for MEMS-based optical applications. Proc Spie 2, 44–53 (2004)

    Google Scholar 

  24. Schaepkens, M., Oehrlein, G.S.: A review of SiO2 etching studies in inductively coupled fluorocarbon plasmas. J. Electrochem. Soc. 148(3), C211–C221 (2001)

    Article  Google Scholar 

Download references

Acknowledgements

This work is supported by the National Natural Science Foundation of China (Grant No. 61574023), the National Natural Science Foundation of China (Grant No. 61404014) and the Open Funds of State Key Laboratory of Vehicle NVH and Safety Technology (Grant Nos. NVHSKL-201608 and NVHSKL-201414).

Author information

Authors and Affiliations

  1. Chongqing Engineering Laboratory of High Performance Integrated Circuits, College of Communication Engineering, Chongqing University, Chongqing, 400044, China

    Kun Cheng, Shengdong Hu, Yuyu Jiang, Qi Yuan, Dong Yang, Ye Huang, Zhi Lin, Xichuan Zhou & Fang Tang

  2. State Key Laboratory of Vehicle NVH and Safety Technology, China Automotive Engineering Research Institute Co., Ltd, Chongqing, 401122, China

    Shengdong Hu & Jianmei Lei

Authors
  1. Kun Cheng
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Shengdong Hu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yuyu Jiang
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Qi Yuan
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Dong Yang
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Ye Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Jianmei Lei
    View author publications

    You can also search for this author in PubMed Google Scholar

  8. Zhi Lin
    View author publications

    You can also search for this author in PubMed Google Scholar

  9. Xichuan Zhou
    View author publications

    You can also search for this author in PubMed Google Scholar

  10. Fang Tang
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Shengdong Hu.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Cheng, K., Hu, S., Jiang, Y. et al. Simulation-based performance analysis of an ultra-low specific on-resistance trench SOI LDMOS with a floating vertical field plate. J Comput Electron 16, 83–89 (2017). https://doi.org/10.1007/s10825-017-0955-1

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10825-017-0955-1

Keywords

Search

Navigation