Search for Optimum and Scalable COSMOS

Abstract

We introduce a novel CMOS device architecture capable of building complementary logic operation using only a single gate stack. The new architecture, named complementary orthogonal stacked MOS (COSMOS), places the n and p-MOSFETs perpendicular to one another under a single gate, integrating them vertically as well as laterally. The COSMOS architecture would not only mean significant savings in active device area of a conventional static CMOS pair, but also significant reductions in RC device parasitics. We demonstrate how the device may be built, operated and optimized for symmetric operation, as well as verifying logic NOT operation via 3D device simulations. COSMOS architecture appears to have peculiar scaling trends such as increasing threshold at reduced gate dimensions. The increase in drive voltages lead to faster operation at the expense of higher static leakage and loss of noise margins.