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Towards Satisfiability Modulo Parametric Bit-vectors

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Abstract

Many SMT solvers implement efficient SAT-based procedures for solving fixed-size bit-vector formulas. These techniques, however, cannot be used directly to reason about bit-vectors of symbolic bit-width. To address this shortcoming, we propose a translation from bit-vector formulas with parametric bit-width to formulas in a logic supported by SMT solvers that includes non-linear integer arithmetic, uninterpreted functions, and universal quantification. While this logic is undecidable, our approach can still solve many formulas that arise in practice by capitalizing on advances in SMT solving for non-linear arithmetic and universally quantified formulas. We provide several case studies in which we have applied this approach with promising results, including the bit-width independent verification of invertibility conditions, compiler optimizations, and bit-vector rewrite rules.

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Notes

  1. Our implementation of the translation does consider the general case since quantified formulas appear in the first of the case studies we discuss in Sect. 5.

  2. On preliminary experiments we observed that higher time limits did not increase the overall success rate of the case studies.

  3. All benchmarks, results, log files, and solver configurations are available at http://cvc4.cs.stanford.edu/papers/CADE2019-JAR/.

  4. At https://github.com/nunoplopes/alive/tree/master/tests/instcombine.

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Authors and Affiliations

  1. Stanford University, Stanford, USA

    Aina Niemetz, Mathias Preiner, Yoni Zohar & Clark Barrett

  2. The University of Iowa, Iowa City, USA

    Andrew Reynolds & Cesare Tinelli

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  1. Aina Niemetz
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  2. Mathias Preiner
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Correspondence to Yoni Zohar.

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This work was supported in part by DARPA (Awards N66001-18-C-4012 and FA8650-18-2-7861), ONR (Award N68335-17-C-0558), NSF (Award 1656926), and the Stanford Center for Blockchain Research.

A preliminary version of this work was published in the proceedings of CADE-27 [24]. The current article includes proofs, concrete axiomatizations for bitwise operators, more details on the evaluation, and a list of conditional inverses for bit-vector literals.

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Niemetz, A., Preiner, M., Reynolds, A. et al. Towards Satisfiability Modulo Parametric Bit-vectors. J Autom Reasoning 65, 1001–1025 (2021). https://doi.org/10.1007/s10817-021-09598-9

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