The complexity gap in the static analysis of cache accesses grows if procedure calls are added

Abstract

The static analysis of cache accesses consists in correctly predicting which accesses are hits or misses. While there exist good exact and approximate analyses for caches implementing the least recently used (LRU) replacement policy, such analyses were harder to find for other replacement policies. A theoretical explanation was found: for an appropriate setting of analysis over control-flow graphs, cache analysis is PSPACE-complete for all common replacement policies (FIFO, PLRU, NMRU) except for LRU, for which it is only NP-complete. In this paper, we show that if procedure calls are added to the control flow, then the gap widens: analysis remains NP-complete for LRU, but becomes EXPTIME-complete for the three other policies. For this, we improve on earlier results on the complexity of reachability problems on Boolean programs with procedure calls. In addition, for the LRU policy we derive a backtracking algorithm as well as an approach for using it as a last resort after other analyses have failed to conclude.

Appendix A: Alternative proof for EXPTIME-completeness of reachability in Boolean programs

Godefroid and Yannakakis [7] claim EXPTIME-hardness for reachability in Boolean programs (Theorem 4), but they refer the reader to a full version of their article, which is available only by request to the authors. We thus provide, in the next subsections, an independent proof of EXPTIME-hardness for Boolean programs.

Note that EXPTIME membership is easily established. A Boolean register machine with procedure calls may be expanded into an equivalent pushdown system, at the cost of exponential blowup: just consider one control location in the pushdown automaton for each control location in the Boolean register machine and each of the (exponentially many) vector of values of the registers; then apply Theorem 1.

1.1 A.1: Succinctly represented problems

We have seen how a reachability problem involving Boolean registers can be expanded into a reachability problem not involving registers, that is, a reachability problem in an oriented graph at the cost of exponential blowup. This is an instance of a more general pattern relating the complexity of problems when they are represented as explicit lists of transitions versus “implicit” list of transitions, for instance involving registers, in the same way that a small Boolean formula is a succinct representation for a much larger explicit truth table.

Galperin and Wigderson [6] studied the complexity of various problems on graphs when these graphs are succinctly represented, by which they mean that graph vertices are labeled by a vector of bits, and the adjacency relation is defined by a Boolean circuit taking as inputs two vectors of bits and answering one bit: whether the vertices labeled by these two vectors are connected. Papadimitriou and Yannakakis [15] generalized their results: a NP-complete problem (respectively, P-complete; NLOGSPACE-complete) problem on explicitly represented graphs, under some fairly permissive condition on the reduction used for showing this completeness property, becomes NEXPTIME-complete (respectively, EXPTIME-complete; PSPACE-complete) on succinctly represented graphs. A well-known example of this phenomenon is the reachability problem: given two vertices in a directed graph, say whether one is reachable from another—it is NLOGSPACE-complete on explicitly represented graphs, and becomes PSPACE-complete on succinctly represented graphs, where it is also known as the reachability problem in implicit-state model checking.

The reachability problem for explicitly represented pushdown systems, which are very close to Boolean register machines with procedure calls but no registers, is known to be P-complete. We can thus hope that it becomes EXPTIME-complete for succinctly represented pushdown systems; however we cannot use Papadimitriou and Yannakakis’ results because they pertain solely to graph problems. We can however follow the same general approach as their hardness proof: analyze the reduction from the acceptance problem for polynomial-time Turing machines to the problem for explicitly represented pushdown systems, which are close to Boolean programs without registers, and construct a reduction from the acceptance problem for exponential-time Turing machines to the problem for succinctly represented pushdown systems, which are close to Boolean programs with registers.

It takes four reduction steps to show that the reachability problem for Boolean register machines with procedure calls and 0 registers is P-hard: (i) from the acceptance problem for polynomial-time Turing machines to the circuit value problem (CVP) Greenlaw et al. [9, 4.2] (ii) from the CVP to the monotone circuit value problem Greenlaw et al. [9, A.1.3] (iii) from the monotone CVP to the emptiness problem for context-free grammars Greenlaw et al. [9, A.7.2] (iv) from emptiness in context-free grammars to reachability in Boolean programs with local variables.

1.2 A.2: Reductions for explicit descriptions

The circuit value problem (CVP) is: given a Boolean circuit, using logical gates $\wedge$, $\vee$, $\lnot$, with known inputs, compute its output. The first reduction step [11] [9, Th. 4.2.2] encodes the bounded deterministic execution of a Turing machine into a circuit in much the same way that one encodes the bounded nondeterministic execution of a Turing machine into a Boolean satisfiability problem: the value $c_{i,j}$ of each cell at each position j in the tape at each point in time $i > 0$ is defined as a function of $c_{i-1,j-1}$, $c_{i-1,j}$ and $c_{i+1,j}$, with a different value whether the read/write head is on the cell; then these values $c_{i,j}$ are encoded into a vector of bits (of size logarithmic in the size of the tape alphabet and the number of control states), and one then obtains a circuit. It then suffices to add initialization for values $c_{0,j}$ of the cells at time 0, and a test for a reachability condition.

The monotone CVP is: given a Boolean circuit, using logical gates $\wedge$ and $\vee$ with known inputs, compute its output. Obviously it is a subset of the general CVP. A general CVP can be encoded into a monotone CVP by using “dual rail encoding” [8] [9, Th. 6.2.2]: each wire b in the original circuit is encoded into two wires $b_0$ and $b_1$, where $b_0$ is 1 if b is 0, 0 if b is 1, and $b_1$ is 1 if b is 1, 0 if b is 0. It is possible to simulate each $\wedge$ or $\vee$ gate of the original circuit by two monotone gates; $\lnot$ gates map to swapping of two wires.

Let us now encode the monotone CVP into the context-free grammar emptiness problem [9, A.7.2, crediting Martin Tompa]. To each wire $w_i$ in the circuit one associates a nonterminal $\nu _i$. If $w_i$ is initialized to 1, then we add a rule $\nu _i \rightarrow \varepsilon$ (meaning that $\nu _i$ accepts the empty word; equivalently one may introduce a nonterminal a and have a rule $\nu _i \rightarrow a$). We add no rule if $w_i$ is initialized to 0. If $w_i$ is defined as $w_j \vee w_k$, then we add two rules $\nu _i \rightarrow \nu _j$ and $\nu _i \rightarrow \nu _k$. If $w_i$ is defined as $w_j \wedge w_k$, then we add a rule $\nu _i \rightarrow \nu _j \nu _k$. The nonterminal $\nu _1$ to test for emptiness is the one that corresponds to the output wire of the monotone circuit.

Finally, let us encode the context-free grammar emptiness problem into the reachability problem for a Boolean program without registers. This is the well-known relationship between context-free grammars and procedure calls in structured programs. Each nonterminal in the grammar becomes a procedure. A derivation rule $L \rightarrow R_1 \dots R_n$ becomes a sequence of calls to th procedures corresponding to nonterminals $R_1$ to $R_n$, starting in the initial control location of the procedure associated with nonterminal L and ending in the final location of that procedure.

1.3 A.3: Lifting reductions to implicitly represented problems

In the above reductions, circuits are described as a list of gates. The first reduction step, from Turing machines to CVP, is however highly repetitive: the same construction is applied for all $i > 0$ and j. We thus use the notion of succinctly described circuit Papadimitriou [14, ch. 20]: wires $w_i$ are identified by their index i written in binary, and gates in the succinctly represented circuits are introduced by rules of the form $C(i,j,k): w_i = w_j \wedge w_k$, $C(i,j,k): w_i = w_j \vee w_k$, $C(i,j): w_i = \lnot w_j$, where C is a condition over the binary encodings of indices i, j, k, itself expressed as a Boolean circuit, that constrains for which indices the gate is created. The notion of succinctly described monotone circuit is defined similarly.

The encodings described above for turning a reachability problem on the execution of a polynomially bounded Turing machine into an explicitly described CVP of polynomial size, then into an explicitly described monotone CVP of polynomial size, can be applied to turn a reachability problem on the execution of an exponentially bounded Turing machine into a succinctly described CVP of polynomial size, then into a succinctly described monotone CVP of polynomial size.⁷

We define similarly the notion of a succinctly represented context-free grammar. A succinct rule $C(i,j,k): \nu _i \rightarrow \nu _j \nu _k$ (for arity 2; other arities are similarly defined), where C is a Boolean circuit over the binary encodings of i, j and k, encodes a family of rules $\nu _i \rightarrow \nu _j \nu _k$ for all i, j, k such that C(i, j, k) returns 1. As with explicitly described monotone CVPs, a succinctly described monotone CVP can be transformed into a succinctly represented context-free grammar emptiness problem.

The variables i, j etc. are binary encodings. For the final reduction to Boolean register machines with procedures, we put these Boolean encodings into the local variables of the Boolean programs.