Abstract
Process monitoring and profile analysis are crucial in detecting various abnormal events in semiconductor manufacturing, which consists of highly complex, interrelated, and lengthy wafer fabrication processes for yield enhancement and quality control. To address real requirements, this study aims to develop a framework for semiconductor fault detection and classification (FDC) to monitor and analyze wafer fabrication profile data from a large number of correlated process variables to eliminate the cause of the faults and thus reduce abnormal yield loss. Multi-way principal component analysis and data mining are used to construct the model to detect faults and to derive the rules for fault classification. An empirical study was conducted in a leading semiconductor company in Taiwan to validate the model. Use of the proposed framework can effectively detect abnormal wafers based on a controlled limit and the derived simple rules. The extracted information can be used to aid fault diagnosis and process recovery. The proposed solution has been implemented in the semiconductor company. This has simplified the monitoring process in the FDC system through the fewer key variables. The results demonstrate the practical viability of the proposed approach.
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Acknowledgments
This research is supported by National Science Council, Taiwan (NSC 99-2221-E-007-047-MY3; NSC 100-2410-H-155-048), and the Ministry of Education (101N2073E1).
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Chien, CF., Hsu, CY. & Chen, PN. Semiconductor fault detection and classification for yield enhancement and manufacturing intelligence. Flex Serv Manuf J 25, 367–388 (2013). https://doi.org/10.1007/s10696-012-9161-4
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DOI: https://doi.org/10.1007/s10696-012-9161-4