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Hard-disk drive read-channel design trade-offs for areal densities beyond 2 Tb/in2

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Abstract

Due to the ever-increasing recording densities, disk-drive read channels are required to operate efficiently at high speeds. With the use of conventional design techniques, a compromise should be made between speed, power, latency and chip area. Improvements of head and media technology and the move from conventional single-track magnetic recording to two-dimensional magnetic recording help increase the areal density of magnetic data storage. Especially for the read channel, a performance gain is achieved by using more powerful coding and signal processing algorithms to mitigate inter-symbol and inter-track interferences. Timing recovery is essential to extract timing information in order to sample read data without a significant bit error, while calibration is performed to cancel the effects of gain and dc offset errors. Speed improvement and power consumption diminution are achieved in the resulting read channel system by using high-speed and power-efficient building blocks based on improved algorithms and pipeline stages to shorten critical paths.

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References

  1. Shimpuku, Y., Okazaki, Y., Ino, H., Yamamoto, K., & Suzuki, H. (2002). A high density and high data transfer rate flexible disk drive for insertion to the PCMCIA type-II slot. IEEE Transactions on Consumer Electronics, 48(2), 195–201.

    Article  Google Scholar 

  2. Hori, Y., Kanai, Y., & Taima, K. (2010). An audiovisual content recorder using a removable hard disk drive. IEEE Transactions on Consumer Electronics, 56(4), 2324–2329.

    Article  Google Scholar 

  3. Seong, Y. K., Choi, Y.-H., Park, J.-A., & Choi, T.-S. (2002). A hard disk drive embedded digital satellite receiver with scene change detector for video indexing. IEEE Transactions on Consumer Electronics, 48(3), 776–782.

    Article  Google Scholar 

  4. Ryu, W., & Song, M. (2010). Design and implementation of a disk energy saving scheme for media players which use hybrid disks. IEEE Transactions on Consumer Electronics, 56(4), 2382–2386.

    Article  Google Scholar 

  5. Thapar, H., & Patel, A. (1987). A class of partial response systems for increasing storage density in magnetic recording. IEEE Transactions on Magnetics, 23(5), 3666–3668.

    Article  Google Scholar 

  6. Hong, J., Wood, R., & Chan, D. (1991). An experimental 180 Mb/sec PRML channel for magnetic recording. IEEE Transactions on Magnetics, 27(6), 4532–4537.

    Article  Google Scholar 

  7. Ndjountche, T. (2018). Amplifiers, Comparators, Multipliers, Filters, and Oscillators. Boca Raton, FL, USA: CRC Press.

    Book  Google Scholar 

  8. Proakis, J. G. (1991). Adaptive equalization for TDMA mobile channel. IEEE Transactions on Vehicular Technology, 40(2), 333–341.

    Article  Google Scholar 

  9. Mueller, K. H., & Müller, M. (1976). Timing recovery in digital synchronous data receivers. IEEE Transactions on Communications, com–24(5), 516–531.

    Article  Google Scholar 

  10. Zheng, N., Venkataraman, K. S., Kavcic, A., & Zhang, T. (2014). A study of multitrack joint 2-D signal detection performance and implementation cost for shingled magnetic recording. IEEE Transactions on Magnetics, 50(6), 1–6.

    Article  Google Scholar 

  11. Ndjountche, T. (2016). Digital Electronics 2: Sequential and Arithmetic Logic Circuits. Hoboken, NJ, USA: ISTE-John Wiley.

    Book  Google Scholar 

  12. Stas, F., & Bol, D. (March 2017). A 0.4V 0.08fJ/cycle retentive true-single-phase-clock 18T flip-flop in 28nm FDSOI CMOS, In Proc. of the IEEE ISCAS, Baltimore, MD, USA, pp. 2779–2782.

  13. Mita, S., Izumita, M., Doi, Nobukazu, & Eto, Y. (1987). Automatic equalizer for digital magnetic recording systems. IEEE Transactions on Magnetics, 23(5), 3672–3674.

    Article  Google Scholar 

  14. Yeh, W.-C., & Jen, C.-W. (2000). High-speed Booth encoded parallel multiplier design. IEEE Transactions on Very Large Scale Integration Systems, 49, 692–701.

    Google Scholar 

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  1. P.ENG., Gatineau, QC, Canada

    Tertulien Ndjountche

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Ndjountche, T. Hard-disk drive read-channel design trade-offs for areal densities beyond 2 Tb/in2. Analog Integr Circ Sig Process (2023). https://doi.org/10.1007/s10470-023-02198-0

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  • DOI: https://doi.org/10.1007/s10470-023-02198-0

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