1 Introduction

Phase-locked loops (PLLs) are commonly utilized for clock generation in high-speed digital systems and local oscillation signals in wireless communication systems. The voltage-controlled oscillator (VCO) is a crucial component of PLLs. The most important requirements for VCOs are low phase noise and wide tuning range. Other essential considerations are low implementation cost and ease of integration. There are two basic structures of VCO: the ring VCO and the LC-VCO. The ring VCO exhibits a wide tuning range, ease of integration, and low cost, but poor phase noise and high-power consumption. While the LC VCO reduces the power dissipation and maintains low phase noise compared to ring VCO [1, 2].

Several types of research have been reported to increase the frequency tuning range of the VCOs. One method is to design multi-core oscillators at different frequencies and enables a single oscillator at a time, but this technique requires an active element and LC circuit for each band [3]. Another technique relies on implementing switching resonators (inductors or capacitors) [4, 5]. Variable inductors using switches to eliminate part of the inductor were presented [6], switched capacitors were also presented [7], and variable MEMS varactor [8]. However, these switching techniques suffer from the needed large area for the LC tank circuit, and the degradation of the Q-factor of the LC tank circuit, because of the series resistance of the switches implemented by the MOS transistor and, consequently, the phase noise of the oscillator becomes poor.

Phase noise improvement is achieved by maximizing the Q-factor of the LC tank circuit where the maximum losses in the tank circuit appear in the on-chip inductors, there are a lot of studies to increase the on-chip inductor Q-factor at the expense of the chip area as changing inductor shape, implementing pattern ground structure under the inductor, or designing shunt (multi-layers) inductor [9,10,11]. Also, another interest is directed to implement high Q-factor active inductors, but this consumed high power, so this aspect is not recommended [12]. In [13] an active LC tank VCO using a differential boot-strapped inductor (DBSI) was designed and achieved poor phase noise, and low output power of − 11 dBm. In [14] the authors used off-chip inductors to design a reconfigurable power amplifier that covers multi-band applications and improves the RF circuit performance. In [15] a compact CMOS linear trans-conductance NMOS PMOS core without a choke inductor to minimize die area was presented and this achieved a phase noise of − 112 dBc/Hz and low output power of − 10.4 dBm. In [16], a wideband NMOS VCO using a digital switching capacitor bank was introduced with a maximum output power of − 6 dBm, and the power dissipated equals 2.37 mW. In [17,18,19] low phase noise and low power dissipation VCOs were designed, in [17] a class-C VCO using a new structure asymmetry inductor was designed in 130 nm CMOS process and achieved an FTR of 34.5% from 2 to 2.9 GHz. While in [18, 19] a tail current technique or filtering technique is used for phase noise improvement.

To implement VCO in medical frequency (low-frequency band) the first selection is the ring oscillator with poor phase noise and high DC power consumption, so the ring oscillator disqualifies in medical application. The second solution is the LC oscillator, LC-tank circuit needs an inductor in the range from 85 to 62 nH for this application, and implementing this inductance value on-chip is impossible due to the balky area size and low-quality factor of the on-chip inductor. So, the proposed VCO offers the best solution for the 393–700 MHz frequency band by using a high Q-factor off-chip inductor. The proposed VCO covers a frequency band from 393 MHz to 4.17 GHz so this can be used in Medical (ISM) bands from 393 to 700 MHz, GSM900, LTE, and Multi-standard applications.

In this work low phase noise and wideband tuning range voltage-controlled power oscillator is proposed, where the frequency tuning range is risen by using six high Q-factor off-chip inductors. Also, using those inductors enhances the VCO performance (tuning range, phase noise, and output power) compared to the conventional inductor. Moreover, three sub-bands are achieved in each band using a single control pin (\({V}_{SW}\)). The paper is organized as follows; Sect. 2 presents the design of the proposed VCO while Post-layout simulation results are introduced in Sect. 3. Section 4 concludes the work.

2 Proposed VCO design

The proposed voltage-controlled power oscillator (VCO) consists of LC-voltage controlled oscillator and two output buffers as displayed in Fig. 1.

Fig. 1
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Schematic diagram of the suggested differential VCO

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2.1 VCO Schematic

The proposed LC-VCO is a complementary cross-coupled PMOS NMOS, that consists of NMOS pair (M1–2), PMOS pair.

(M3–4), PMOS current source (M5) that has low flicker noise compared to NMOS current source, feedback capacitor Cfp that enhances the phase noise. PMOS current source is preferred over the NMOS current sink. PMOS current source is generally utilized because the PMOS transistor has less noise flicker than the NMOS transistor [20]. The frequency tuning range is achieved by the varactor capacitor Cv, the improved switching capacitor Csw to divide each band into three sub-bands, and the high-quality factor off-chip inductor L as shown in Fig. 1. The enhanced varactor composes of a MOS varactor and MIM capacitor connected in series to improve the phase noise. In the first half cycle of the oscillation, the transistors M3 and M2 are in the on state, M4 and M1 are in the off state, and the current passes through the off-chip from left to right, in the second half cycle, the current direction in the resonator is opposite from right to left. The VCO core is followed by two output buffers, each one consisting of two NMOS transistors, and a chock off-chip inductor connected as a cascode amplifier to raise the output power. The buffer is a cascode amplifier because the cascode configuration achieves a high gain and high output power with good isolation over a wide bandwidth, mainly the cascade amplifier is used to increase the dBm output power for voltage-controlled power oscillator applications [21]. Capacitor Co that implemented on-chip and its value is determined to maximize the output power of the VCO. The component values of the proposed VCO circuit are described in Table 1.

Table 1 Values of the circuit elements of the proposed VCO in Fig. 1
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2.2 Proposed LC-tank circuit

The spiral inductor usually encounters a low-quality factor, especially the high inductance value, therefore VCO design at the low-frequency band as Medical-band, GSM900, LTE, and Multi-standard applications or beyond is very challenging. The proposed method employs a high-quality factor off-chip inductors and then integrates it into the VCO using bond wire, therefore the proposed method alleviates the above problem of poor Q-factor and gives an alternative design approach to VCO at the low-frequency band. The proposed LC-tank circuit composes of an off-chip inductor, a switching varactor to achieve triple sub-bands, and a tuning varactor to tune between a minimum and maximum oscillation frequencies as illustrated in Fig. 1. The off-chip inductor is selected from six different values to cover the wide tuning range. The selected off-chip inductors have high-quality factors, and high self-resonance frequency so they solve the problems that appear in on-chip inductors. The bonding wire equivalent circuit is considered as Cpad that represents the pad capacitance and Lbond that represents the inductance of bonding wire as displayed in Fig. 1, the value of Lbond is about 1nH/mm [12], and the quality (Q) factor of bonding wire increases with frequency, where the Q-factor of bonding wire equal 50 at 1 GHz and equal 100 at 5 GHz more details about bonding wire in [14].

The discrete inductors are usually specified by the quality factor (Q), Tolerance (T), Self-Resonance Frequency (SRF), and Dimensions (D). Table 2 illustrates the manufacturing part numbers and specification parameters of the used discrete inductors. To ensure accurate results and take into consideration all the parasitic effects, the real model of the discrete components is used by inserting the manufacture SNP file (Measured S-parameters file) of the selected discrete components in the simulation tool. As clear in Table 2, all the chosen inductors have a self-resonance frequency above twice the operating frequency of the proposed VCO. Figure 2 displays the electrical model of an off-chip inductor where Lvar is the inductance, (C) represents the coupling capacitor, and R is loss resistance.

Table 2 Discrete components specification parameters used in the proposed design
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Fig. 2
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Electrical model of the off-chip inductor

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3 Post –layout simulation results

The proposed LC VCO is designed using 130 nm CMOS process. Advanced Design System (ADS) for circuit simulation, and Cadence Design Systems software for circuit layout and physical verifications. The layout of the suggested voltage-controlled oscillator is illustrated in Fig. 3, where the VCO core area equals 0.07 \({\mathrm{mm}}^{2}\), while the total chip area included the two output buffers, and pads is 0.437 \({\mathrm{mm}}^{2}\). The phase noise of the proposed VCO using the high Q-factor off-chip inductor is improved by 4–25 dB compared to the VCO that uses a conventional inductor provided by technology, as displayed in Fig. 4. The proposed VCO is biased from a supply voltage (VDD) of 1.1 V and draws a current of 1.37 mA while each output buffer draws 3.3 mA from 1.2 V supply voltage (VBuf) and Vbias is buffer biasing voltage and set to 0.62 V. In the proposed VCO VB is the biasing voltage of current source (M5) and connected to ground.

Fig. 3
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Layout of the proposed differential VCO

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Fig. 4
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Phase noise of the proposed VCO using off-chip inductor and conventional inductor when Vsw equals 1 V

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The proposed VCO has a frequency tuning range (FTR) of 166% from 393 MHz to 4.17 GHz as shown in Fig. 5 (a, b, c, d, e, f. This excellent tuning range is divided into six bands according to the inductor value (L) and each band is divided into three bands and controlled using switching voltage. The phase noise of the proposed VCO at 1 MHz offset changes from − 111 to − 127 dBc/Hz as plotted in Fig. 6.

Fig. 5
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Frequency tuning range with control voltage of the proposed VCO

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Fig.6
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Phase noise (PN) against oscillation frequency of the proposed VCO

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Leeson’s formula predicts the phase noise at an offset frequency Δf from the oscillation frequency fosc is specified by [22];

$$PN=10.Log \left\{\frac{2FkT}{{P}_{S}}.\left[1+{\left(\frac{{f}_{osc}}{2{Q}_{L}\Delta f}\right)}^{2}\right].\left(1+\frac{{\Delta f}_{1/{f}^{3}}}{\left|\Delta f\right|}\right)\right\}$$
(1)

Where F, k, T, Ps, and Q, are the noise factor, the Boltzmann’s constant, the absolute temperature, the average power dissipated, and the tank circuit quality factor, respectively. As clear in Eq. (1) when the tank circuit quality factor (Q) grows the oscillator phase noise will be enhanced.

As illustrated in Table 2, the quality factor of the selected inductor is at least three times of the conventional on chip inductor one. Study the case when the oscillation frequency equals 500 MHz and using Eq. (1) the phase noise at 1 MHz offset using the suggested VCO is enhanced by 16.5 dB compared to the technology inductor VCO.

The simulated figure of merit (FoM) of the suggested VCO versus oscillation frequency is plotted in Fig. 7, the best figure of merit is -193 dBc/Hz. The dBm output power of the proposed VCO versus oscillation frequency is illustrated in Fig. 8, with the maximum dBm value being 4.2dBm. Figure 9 shows the frequency tuning range of the stacked inductor VCO while the phase noise and figure of merit of the stacked inductor VCO are displayed in Fig. 10. The time-domain of differential output signals for the proposed VCO is shown in Fig. 11, the peak-to-peak output signal equals 1.2 V at \({V}_{Control}=1V\), and \({V}_{sw}=1V\) that means an oscillation frequency of 820 MHz.

Fig. 7
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Figure of merit (FoM) against oscillation frequency of the proposed VCO

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Fig. 8
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dBm output power of the suggested VCO against oscillation frequency

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Fig. 9
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Frequency tuning range with control voltage of the stacked VCO

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Fig. 10
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Phase noise and figure of merit against oscillation frequency of the stacked inductor VCO

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Fig. 11
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Time domain of output signals for the proposed VCO at oscillation frequency of 820 MHz

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Table 3 illustrates the frequency bands, phase, and output of the proposed VCO based on the inductance value in the LC tank circuit. The suggested differential VCO displays better or comparable performances than the reported VCOs implemented using the CMOS process in terms of FTR (%), Phase noise, \({P}_{DC}(mW)\), Area (\({\mathrm{mm}}^{2}\)), and FoM. The proposed differential VCO performance and comparison with the state-of-the art is illustrated in Table 4.

Table 3 Frequency band selection based on off chip inductance value
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Table 4 Performance comparison of VCO designed in CMOS Process
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4 Conclusion

A low phase noise wide tuning range VCO is introduced. The proposed technique eliminates the detrimental effects of a conventional switched method on VCOs phase noise. By using high Q-factor inductors and feedback capacitors across PMOS transistors the phase noise of the proposed VCO is improved by 15 dB compared to conventional inductor VCO.

The proposed differential VCO achieves a wide frequency tuning range of 166% divided into six bands by using different inductor banks. Also, the proposed VCO consumes 1.5 mW, and achieves a low phase noise of − 127, and FOM of − 193 dBc/Hz, Finally, the chip area of the proposed VCO is 0.437 \({\mathrm{mm}}^{2}\).