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A 2.55-mW on-chip passive balun-LNA in 180-nm CMOS

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Abstract

In this paper, an on-chip planar balun and a common-gate (CG) low-noise amplifier (LNA) employing a multiple feedback structure is presented. The planar interleaved balun is characterized through electromagnetic (EM) simulations using Advanced Design System (ADS) Momentum. A new lumped circuit model of the balun is created for use in transient simulations. CG-LNA employs \(g_m\)-boosting and positive feedback structures to reduce the high noise figure (NF) of the traditional CG-LNA. The combined blocks achieve a minimum NF of 5.5 dB and an AC gain of 18.54 dB in post-layout simulations. The balun and LNA blocks are designed in a 180 nm CMOS technology using 1Poly6Metal (1P6M) layers. Simulation results are presented for post-layout and schematic cases. The total power consumption of the the circuit is 2.55 mW with 1.8 V nominal power supply. Furthermore, a time-domain UWB pulse simulation is done to confirm the operation of the blocks combined. These can be used to form the initial stages of an UWB receiver.

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Data Availability Statement

Data sharing is not applicable to this article as no datasets were generated or analysed during the current study.

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The authors did not receive support from any organization for the submitted work.

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Authors and Affiliations

  1. Faculty of Electrical Engineering and Information Technology, RWTH Aachen University, 52074, Aachen, Germany

    Atakan Aydoğdu

  2. Department of Electrical and Computer Engineering, Technical University of Munich, 80333, Munich, Germany

    Deniz Tomar

  3. Department of Electrical and Electronics Engineering, İstanbul Bilgi University, 34060, İstanbul, Turkey

    Okan Zafer Batur

  4. Department of Electrical and Electronics Engineering, Boğaziçi University, 34342, İstanbul, Turkey

    Günhan Dündar

Authors
  1. Atakan Aydoğdu
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  2. Deniz Tomar
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  3. Okan Zafer Batur
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  4. Günhan Dündar
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Correspondence to Atakan Aydoğdu.

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Aydoğdu, A., Tomar, D., Batur, O.Z. et al. A 2.55-mW on-chip passive balun-LNA in 180-nm CMOS. Analog Integr Circ Sig Process 111, 223–234 (2022). https://doi.org/10.1007/s10470-022-01997-1

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  • DOI: https://doi.org/10.1007/s10470-022-01997-1

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