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A Novel Low Power 4:2 Compressor using FinFET Devices

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Abstract

The compressor is widely used in multi-operand addition, and multiplication. Enhancing the performance of the compressor affects the capability of the multiplier, which influences the efficiency of the digital signal processor. Therefore, improving the performance of the compressor has attracted the interest of the researchers. Metal oxide semiconductor field effect transistor (MOSFET) has been replaced by fin-shaped field effect transistor (FinFET), owing to its superior channel control, ease of fabrication, high scalability, and ability to tackle the short channel effects (SCEs). In this paper, a novel structure 4:2 compressor is proposed, and analyzed. The proposed 4:2 compressor is simulated, and compared with the existing 4:2 compressors using Cadence’s Virtuoso tool at 16 nm FinFET technology. The effect of process, and power supply voltage (VDD) variations have been investigated. The proposed compressor has a lower value of power dissipation, power delay product (PDP), and energy delay product (EDP) as compared to the existing compressors. Simulation results show that the proposed compressor is improving the power dissipation by 48.43%, PDP by 45.43%, and EDP by 42.25% as compared to the best reported available design.

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References

  1. Taheri, M., Arasteh, A., Mohammadyan, S., Panahi, A., & Navi, K. (2020). A novel majority based imprecise 4:2 compressor with respect to the current and future VLSI industry. Microprocessors and Microsystems, 73, 102962.

    Article  Google Scholar 

  2. Kumar, M., & Nath, J. (2017). Design of an energy efficient 4–2 compressor. IOP Conference Series: Materials Science and Engineering, 225(1), 012136.

    Article  Google Scholar 

  3. Kumar, M., & Nath, J. (2017). Performance analysis comparison of 4–2 compressors in 180nm CMOS technology. IOP Conference Series: Materials Science and Engineering, 225(1), 1012138.

    Google Scholar 

  4. Nehra, V., Prajapati, S., Tankwal, P., Zilic, Z., Kumar, T. N., & Kaushik, B. K. (2019). Energy-efficient differential spin hall MRAM-based 4–2 magnetic compressor. IEEE Transactions on Magnetics, 56(1), 1–1.

    Article  Google Scholar 

  5. Shirinabadi, F. S., & Reshadinezhad, M. R. (2019). A new twelve-transistor approximate 4:2 compressor in CNTFET technology. International Journal of Electronics, 106(5), 691–706.

    Article  Google Scholar 

  6. Bagherizadeh, M., Moaiyeri, M. H., & Eshghi, M. (2019). A high-performance 5-to-2 compressor cell based on carbon nanotube FETs. International Journal of Electronics, 106(6), 912–927.

    Article  Google Scholar 

  7. Taheri, M., Sharifi, F., Shafiabadi, M., Mahmoodi, H., & Navi, K. (2019). Spin-based imprecise 4–2 compressor for energy-efficient multipliers. SPIN, 9(3), 1950011.

    Article  Google Scholar 

  8. Agarwal, S., Harish, G., Balamurugan, S., & Marimuthu, R. (2018). Design of high speed 5:2 and 7:2 compressor using nanomagnetic logic. In International symposium on VLSI design and test, Singapore, pp. 49–60.

  9. Xu, C., Zheng, Y., Niu, D., Zhu, X., Kang, S. H., & Xie, Y. (2015). Impact of write pulse and process variation on 22 nm FinFET-based STT-RAM design: A device-architecture co-optimization approach. IEEE Transactions on Multi-Scale Computing Systems, 1(4), 195–206.

    Article  Google Scholar 

  10. Momeni, A., Han, J., Montuschi, P., & Lombardi, F. (2014). Design and analysis of approximate compressors for multiplication. IEEE Transactions on Computers, 64(4), 984–994.

    Article  MathSciNet  Google Scholar 

  11. Thapliyal, H., Mohammad, A., Kumar, S. D., & Sharifi, F. (2017). Energy-efficient magnetic 4–2 compressor. Microelectronics Journal, 67, 1–9.

    Article  Google Scholar 

  12. Pishvaie, A., Jaberipur, G., & Jahanian, A. (2014). High-performance CMOS (4:2) compressors. International Journal of Electronics, 101(11), 1511–1525.

    Article  Google Scholar 

  13. Pishvaie, G. J., & Jahanian, A. (2012). Improved CMOS 4:2 compressor designs for parallel multipliers. Computers & Electrical Engineering, 38(6), 1703–1716.

    Article  Google Scholar 

  14. Baran, D., Aktan, M., & Oklobdzija, V. G. (2010). Energy efficient implementation of parallel CMOS multipliers with improved compressors. In Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, pp. 147–152.

  15. Arasteh, A., Moaiyeri, M. H., Taheri, M., Navi, K., & Bagherzadeh, N. (2018). An energy and area efficient 4:2 compressor based on FinFETs. Integration, 60, 224–231.

    Article  Google Scholar 

  16. Sharma, V. K., Pattanaik, M., & Raj, B. (2014). ONOFIC approach: Low power high speed nanoscale VLSI circuits design. International Journal of Electronics, 101(1), 61–73.

    Article  Google Scholar 

  17. Sharma, V. K., Pattanaik, M., & Raj, B. (2015). INDEP approach for leakage reduction in nanoscale CMOS circuits. International Journal of Electronics, 102(2), 200–215.

    Article  Google Scholar 

  18. Akbari, O., Kamal, M., Afzali-Kusha, A., & Pedram, M. (2017). Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Transactions on Very Large Scale Integration VLSI Systems, 25(4), 1352–1361.

    Article  Google Scholar 

  19. Almeida, R. B., Marques, C. M., Butzen, P. F., Silva, F. R., Reis, R. A., & Meinhardt, C. (2018). Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies. Microelectronics Reliability, 88, 196–202.

    Article  Google Scholar 

  20. Dutta, T., Pahwa, G., Agarwal, A., & Chauhan, Y. S. (2017). Impact of process variations on negative capacitance FinFET devices and circuits. IEEE Electron Device Letters, 39(1), 147–150.

    Article  Google Scholar 

  21. Moaiyeri, M. H., Sabetzadeh, F., & Angizi, S. (2018). An efficient majority-based compressor for approximate computing in the nano era. Microsystem Technologies, 24(3), 1589–1601.

    Article  Google Scholar 

  22. Huang, R., Jiang, X. B., Guo, S. F., Ren, P. P., Hao, P., Yu, Z. Q., Zhang, Z., Wang, Y. Y., & Wang, R. S. (2017) Variability-and reliability-aware design for 16/14nm and beyond technology. In 2017 IEEE international electron devices meeting (IEDM), pp. 12–14.

  23. Bae, M. H., & Yun, I. (2020). Impact of process variability in junctionless FinFETs due to random dopant fluctuation, gate work function variation, and oxide thickness variation. Semiconductor Science and Technology, 35, 035015.

    Article  Google Scholar 

  24. Li, Y., Yu, S. M., & Chen, H. M. (2007). Process-variation-and random-dopants-induced threshold voltage fluctuations in nanoscale CMOS and SOI devices. Microelectronic Engineering, 84(9–10), 2117–2120.

    Article  Google Scholar 

  25. Sabetzadeh, F., Moaiyeri, M. H., & Ahmadinejad, M. A. (2019). majority-based imprecise multiplier for ultra-efficient approximate image multiplication. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(11), 4200–4208.

    Article  Google Scholar 

  26. Xiong, S., & Bokor, J. (2003). Sensitivity of double-gate and FinFET Devices to process variations. IEEE Transactions on Electron Devices, 50(11), 2255–2261.

    Article  Google Scholar 

  27. Nam, H., & Shin, C. (2014). Impact of current flow shape in tapered (versus rectangular) FinFET on threshold voltage variation induced by work-function variation. IEEE Transactions on Electron Devices, 61(6), 2007–2011.

    Article  Google Scholar 

  28. Agarwal, S., Pandey, R. K., Johnson, J. B., Dixit, A., Bajaj, M., Furkay, S. S., Oldiges, P. J., & Murali, K. V. (2013). Ab initio study of metal grain orientation-dependent work function and its impact on FinFET variability. IEEE Transactions on Electron Devices, 60(9), 2728–2733.

    Article  Google Scholar 

  29. Minhaj, E. H., Esha, S. R., Adnan, M. M., & Dey, T. (2018). Impact of channel length reduction and doping variation on multigate FinFETs. In IEEE international conference on advancement in electrical and electronic engineering (ICAEEE), pp. 1–4.

  30. Bhattacharya, D., & Jha, N. K. (2014). FinFETs: From devices to architectures. Advances in Electronics, 2014, 365689.

    Article  Google Scholar 

  31. Hayashida, T., Endo, K., Liu, Y., Ouchi, S. I., Matsukawa, T., Mizubayashi, W., Migita, S., Morita, Y., Ota, H., Hashiguchi, H., & Kosemura, D. (2012). Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance. IEEE Transactions on Electron Devices, 59(3), 647–653.

    Article  Google Scholar 

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  1. School of Electronics & Communication Engineering, Shri Mata Vaishno Devi University, Katra, 182320, India

    Anjum Riaz & Vijay Kumar Sharma

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  1. Anjum Riaz
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  2. Vijay Kumar Sharma
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Correspondence to Vijay Kumar Sharma.

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Riaz, A., Sharma, V.K. A Novel Low Power 4:2 Compressor using FinFET Devices. Analog Integr Circ Sig Process 112, 127–139 (2022). https://doi.org/10.1007/s10470-022-01989-1

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