Abstract
This paper presents the power and delay comparison of 7:3 compressor circuit designed using three different architectures of XOR gate which are based upon mirror circuit, 4-transistor, (4-T) and transmission gate (TG). The compressors have been implemented in transistor level at 180 nm technology and the functionality is verified in Cadence-spectre. Among the 7:3 compressors, the design utilizing the TG-based XOR gate is exhibiting least power consumption and the least delay is exhibited by the design which is based upon mirror circuit-based XOR gate.
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References
Dandapat A, Goshal S, Sarkar P, Mukhopadhyay D (2010) A 1.2 ns 16 × 16 bit binary multiplier using high speed compressors. Int J Elect Electron Eng 4: 485–490
Menon R, Radhakrishnan D (2006) High performance 5:2 compressor architecture. In: IEE Proc. Circuits, Devices, Syst. vol 153, pp 447–452
Veeramachaneni S, Krishna KM, Avinash L, Puppala SR, Srinivas MB (2007) Novel architecture for high-speed and low power 3-2, 4-2, and 5-2 compressors. In: IEEE Int. Conf. VLSI Design, pp 324–329
Siliveru A, Bharati M (2013) Design of compressor based multiplier using degenerate pass transistor logic. Int J Eng Trends Technol 4:896–900
Lakshmi GS, Fatima K, Madhavi BK (2016) Compressor based 8 × 8 bit vedic multiplier using reversible logic. In: Int. Conf. Devices, Circuits, Syst. pp 174–178 (2016)
Ravi N, Prasad TJ, Umamahesh M, Rao TS (2010) Performance evaluation of high speed compressors for high speed multipliers using 90 nm technology. In: Recent Adv. Space Technol. Serv. Climate Change. pp 189–193 (2010)
Marimuthu R, Rezinold YE, Mallick PS (2017) Design and analysis of multiplier using appropriate 15-4 compressor. IEEE Access 5:1027–1036
Kumar S, Kumar M (2014) 4-2 Compressor design with new XOR-XNOR module. In: Int. Conf. Adv. Comput. Comm. Technol. pp 106–111 (2014)
Uyemura JP (2002) CMOS logic circuit design. Kluwer Academic Publishers
Multiple Operand Addition. https://pubweb.eng.utah.edu/~cs6830/Slides/chap3x2.pdf
Navi K, Maeen M, Foroutan V, Timarchi S, Kavehei O (2009) A novel low-power full-adder cell for low voltage. Integration, VLSI J 42:457–467
Shams AM, Darwish TK, Bayoumi MA (2002) Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Trans VLSI Syst 10:20–29
Acknowledgements
This work is supported by Ministry of Electronics and Information Technology, Government of India, under Visvesvaraya Ph.D. Scheme.
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Appendix
Appendix
The Karnaugh map for the output \( q_{b1} \) is shown below:
Considering the circled minterms:
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Ahmed, R.U., Saha, P. (2020). Power and Delay Comparison of 7:3 Compressor Designs Based on Different Architectures of XOR Gate. In: Ranganathan, G., Chen, J., Rocha, Á. (eds) Inventive Communication and Computational Technologies. Lecture Notes in Networks and Systems, vol 89. Springer, Singapore. https://doi.org/10.1007/978-981-15-0146-3_44
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DOI: https://doi.org/10.1007/978-981-15-0146-3_44
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