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A reusable stage based reduced comparator count binary search ADC

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Abstract

A 4- bit reusable stage based asynchronous binary search analog to digital converter (ADC) with a smart switching network, and reduced comparator count is presented in this paper. The proposed ADC uses asynchronous logic to activate comparators sequentially while switching network is used to provide reference voltages for selected comparators. In the extended version, the 6-bit ADC is designed using only \((\mathrm{N}+1)\) comparators instead of \(2^{(N)}-1\) and (2N − 1) as used in conventional approach. The simulation results of 4 bit ADC confirms that the design achieves conversion speed of 500 MSPS with power consumption of 1.63 mW when operated on 1.8 V supply with SNR, SFDR and ENOB as 22.5 dB, 32.4 dBc and 3.8 bits while for 6 bit the SNR, SFDR and ENOB are 34.96 dB, 42 dBc and 5.56 bits respectively with 0.35 mW of power dissipation. The Walden FOM for proposed 4 bit and 6 bit ADC design are 0.21 pJ/conversion-step and 24.7 fJ/conversion-step respectively.

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Acknowledgements

The author would like to thank MeitY (Ministry of Electronics and Information Technology, Govt. of India) for providing support under SMDP-C2SD (Special Manpower Development Program for Chips to System Design) project.

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  1. Electronics and Communication Engineering, Microelectronics Division, Indian Institute of Information Technology Allahabad, Prayagraj, Uttar Pradesh, India

    Dipti, Rohit Joshi, Prasanna Kumar Misra & Manish Goswami

  2. Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, India

    Sajai Vir Singh

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Correspondence to Manish Goswami.

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Dipti, Singh, S.V., Joshi, R. et al. A reusable stage based reduced comparator count binary search ADC. Analog Integr Circ Sig Process 105, 33–43 (2020). https://doi.org/10.1007/s10470-020-01686-x

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