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A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

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Abstract

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.

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Acknowledgments

This work was supported by the National Science Council, Taiwan, Republic of China. The authors would like to acknowledge fabrication support provided by National Chip Implementation Center (CIC). The author would also like to thank Chien-Kuo Huang for their assistance with simulation and layout.

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  1. Department of Electrical Engineering, National Formosa University, No. 64, Wunhua Road, Huwei Township, Yunlin County, 63201, Taiwan, ROC

    Chi-Chang Lu

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Correspondence to Chi-Chang Lu.

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Lu, CC. A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique. Analog Integr Circ Sig Process 81, 137–143 (2014). https://doi.org/10.1007/s10470-014-0374-1

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  • DOI: https://doi.org/10.1007/s10470-014-0374-1

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