# Two-step switching scheme for SAR ADC with high energy efficiency

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## Abstract

The paper presents two high energy-efficiency switching schemes for the successive approximation register (SAR) analogue-to-digital converter (ADC). The first scheme is a part of the second one. The new switching schemes achieves no switching energy consumption in the first three comparison, and need no reset energy. Thus, compared with the conventional SAR architecture, 99.23 and 99.42% reduction in switching energy is achieved respectively. Moreover, the total scheme achieves an 86.7% reduction in unit capacitor number by its special architecture.

## Keywords

SAR ADC Energy-efficiency switching scheme Reset energy Capacitor saving## 1 Introduction

Successive approximation register (SAR) analogue-to-digital converter (ADC) is a popular candidate for medium-precision and medium-speed ADC used in wireless sensor networks and medical instrumentation applications. Compared with other kinds of ADCs, it has advantages such as high-energy efficiency, switching feature and being amenable to CMOS process scaling. In SAR ADC with capacitor DACs, the energy consumption during the capacitor switching plays a leading role in the overall power consumption. Therefore, a variety of switching schemes have been proposed to reduce the power consumption [1, 2, 3, 4, 5].The tri-level switching scheme [1], monotonic scheme [2], modified merged capacitor switching (MCS) scheme [3] and novel energy-efficient capacitor switching scheme [4] achieve 81.2, 87.5, 93.7 and 98.8% reductions in average switching energy, respectively, compared with the conventional conversion scheme [2]. However, in some presented switching scheme, the reset energy is nonnegligible, even higher than the switching energy (Fig. 4(5)). Thus, it is indispensable to take both the switching energy and the reset energy into consideration.

In this letter, a new two-step switching scheme is proposed, while its first step switching scheme can also be an energy-efficient switching scheme solely. The proposed two-step scheme and its first step scheme achieve 99.42 and 99.23% reduction in average switching energy, respectively, and have no reset energy consumption. Moreover, 86.7 and 75% reduction in unit capacitor number over the conventional scheme are also achieved.

## 2 Energy analyses

For most of the switching energy is consumed in the first several bit cycles, it is a key point to reduce the switching energy of the first several bit cycles to zero, Analyze the switching energy as follows:

The subscript “i” represents the quantities of the unchanged capacitors, while “j” represents the changed capacitors. The subscript “y” represents the quantities after the switching, and “x” represents the quantities before the switching.

_{j}is the same, so:

There are several ways to let E = 0.

### 2.1 The first way

### 2.2 The second way

If the bottom plate voltage of all the capacitors are changed and changed in the same quantity (\( \sum\nolimits_{j} {C_{j} } = C_{tot} ,\,\,\sum\nolimits_{i} {C_{i} } = 0,\,\, {\text{k}} = 1) \)). It is easy to get \( {\text{E}} = 0 \).

### 2.3 The third way

It is easy to get \( {\text{E}} = 0 \), but it is difficult to find a special voltage distribution [6].

### 2.4 The fourth way

In some cases, we can get a negative E, so it’s seems that the zero switching energy consumption can be achieved by \( E_{P} + E_{n} = 0 \) (\( E_{P } \) is the energy consumption of P-DAC, and \( E_{N} \) is the energy consumption of N-DAC). But, a special voltage distribution should be applied [6].

## 3 Proposed switching scheme

### 3.1 The first step

_{cm}, where V

_{cm}equals to half of the voltage reference V

_{ref}. ‘1’, ‘1/2’ and ‘0’ represent the voltage reference V

_{ref}, V

_{cm}and ground (GND). After sampling, we can get the MSB (D1) directly by comparing the inputs without any switching. Based on the MSB (D1), the voltage of all the bottom-plates of the lower input referred capacitor array are increased by V

_{cm}, being changed to [V

_{ref}, V

_{ref}, V

_{cm}, V

_{cm}]. The other capacitor array remain unchanged. Thus, the MSB-1(D2) is obtained, and no switching energy is consumed in this operation due to “the first way”. During the third bit cycle, if D2 and D1 are not equal, the side with [V

_{cm}, V

_{cm}, GND, GND] is changed to [V

_{cm}, V

_{cm}, V

_{cm}, V

_{cm}], while the other side remain unchanged. If D2 is equal to D1, the side with [V

_{cm}, V

_{cm}, GND, GND] is changed to [GND, GND, GND, GND]. Due to “the second way”, this operation consumes zero switching energy. So far, there is no switching energy consumption in the first three bit-cycles with the proposed scheme.

In the following bit cycles, a single-side switching method is applied. As shown in Fig. 1, the side with [V_{cm}, V_{cm}, V_{cm}, V_{cm}] or [GND, GND, GND, GND] is always unchanged, and the other side capacitor array switch with only two reference voltages, following the scheme proposed by [3].

### 3.2 The second step

_{rest}. During the first step, all the plates of the second part capacitor array are set to V

_{cm}. When the first step is complete, connect the second part capacitor array with the DAC that worked in the first step, turn off S1, S2, S3 and turn on S4, as shown in Fig. 3 for example. Then, we can get the last 4 bits by the scheme proposed by [3]. The number of Crest can be get by the following equations [7].

Compared with the symmetrical architecture, the proposed one only need one capacitor-based DAC in the second part, which achieves nearly 50% reduction in the unit capacitor number.

S1–S5 will affect the accuracy of the ADC in two respects.

ΔV_{DAC1_real} and ΔV_{DAC2_real} are the real upper plate voltage change of the capacitor array DAC, and ΔV_{DAC1}, ΔV_{DAC1} are the theoretical value. C_{Sx} is the stray capacitance of switch. C_{allx} is the total capacitance of the capacitor array. In the second step, both plates of C1 are floating, so the effect on C1 can be ignored. Minish the array of the switching tube can decrease the stray capacitance. If necessary, a digital calibration could be introduced.

The second respect, when the switches move, the leak current will affect the DAC’s voltage. Using the transmission gate with both N-MOS and P-MOS and choosing a reasonable aspect ratio could minimize the leak current.

## 4 Reset energy

_{cm}due to “the first way”. However, it will result in a huge energy consumption if we reset the first part capacitor array to the original state in the next moment. To reduce the reset energy, we use a scheme shown in Fig. 4. Figure 4(1) shows a capacitor array of the first part, which we cannot make sure the voltage distribution on its bottom plates. Turn off S5 and all the switches between the bottom plates and the reference voltage, and short the MSB and LSB respectively [8]. Then, the MSB is changed to V

_{cm}while the LSB is changed to Gnd. Due to “the second way”, this operation draw no energy from the reference voltage. Next, the MSB and LSB sample the input respectively. When the sampling is finished, S5 is turned on, and a new SAR cycle begins. Since both the up-plate voltage of the MSB and LSB is V

_{in}, there is no charge redistribution in this operation, which means there is no energy consumption. From the above, the reset energy is reduced to zero theoretically.

## 5 Simulation

_{ref}

^{2}, which achieves a 99.23% reduction over the conventional architecture. When both the two proposed parts is applied, the average switching energy is only 7.91CV

_{ref}

^{2}. Besides the switching energy saving, both the two proposed scheme have no reset energy while (Fig. 4(5)) consume a huge energy in resetting. In the respect of unit capacitor saving, the number of unit capacitor used in the two proposed scheme is 512 and 272 respectively, which is 4096 in the conventional architecture, achieving 75 and 86.7% reduction.

Comparison of several switching schemes for 10-bit ADC

Switching scheme | Switching energy (CV | Switching energy saving | Reset energy (CV | Total energy saving | Unit capacitor saving |
---|---|---|---|---|---|

Conventional [2] | 1363.33 | Reference | 0 | Reference | Reference |

VCM-monotonic [9] | 15.8 | 93.8% | 31.2 | 81.6% | 50% |

Vcm-based [10] | 170.2 | 87.5% | 0 | 87.5% | 50% |

MSB-split-VCMbased [3] | 106.42 | 92.2% | 0 | 92.2% | 50% |

Tri-level [1] | 42.42 | 96.9% | 0 | 96.9% | 75% |

Proposed-part 1 | 10.54 | 99.23% | 0 | 99.23% | 75% |

Proposed-total | 7.91 | 99.42% | 0 | 99.42% | 86.7% |

## 6 Conclusion

Two energy-efficient and area-efficient switching scheme is presented in this paper. The switching energy is reduced by 99.23 and 99.42% respectively, while no reset energy is consumed. The number of unit capacitor is reduced by 75 and 86.7%. Therefore, it is applicable to use the proposed schemes in the biomedical area.

## Notes

### Acknowledgements

This work was supported by the National Natural Science Foundation of China (61625403, 61504104).

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