Two-step switching scheme for SAR ADC with high energy efficiency

  • Chenggao Zhang
  • Shubin Liu
  • Zhangming Zhu
Open Access
Mixed Signal Letter


The paper presents two high energy-efficiency switching schemes for the successive approximation register (SAR) analogue-to-digital converter (ADC). The first scheme is a part of the second one. The new switching schemes achieves no switching energy consumption in the first three comparison, and need no reset energy. Thus, compared with the conventional SAR architecture, 99.23 and 99.42% reduction in switching energy is achieved respectively. Moreover, the total scheme achieves an 86.7% reduction in unit capacitor number by its special architecture.


SAR ADC Energy-efficiency switching scheme Reset energy Capacitor saving 

1 Introduction

Successive approximation register (SAR) analogue-to-digital converter (ADC) is a popular candidate for medium-precision and medium-speed ADC used in wireless sensor networks and medical instrumentation applications. Compared with other kinds of ADCs, it has advantages such as high-energy efficiency, switching feature and being amenable to CMOS process scaling. In SAR ADC with capacitor DACs, the energy consumption during the capacitor switching plays a leading role in the overall power consumption. Therefore, a variety of switching schemes have been proposed to reduce the power consumption [1, 2, 3, 4, 5].The tri-level switching scheme [1], monotonic scheme [2], modified merged capacitor switching (MCS) scheme [3] and novel energy-efficient capacitor switching scheme [4] achieve 81.2, 87.5, 93.7 and 98.8% reductions in average switching energy, respectively, compared with the conventional conversion scheme [2]. However, in some presented switching scheme, the reset energy is nonnegligible, even higher than the switching energy (Fig. 4(5)). Thus, it is indispensable to take both the switching energy and the reset energy into consideration.

In this letter, a new two-step switching scheme is proposed, while its first step switching scheme can also be an energy-efficient switching scheme solely. The proposed two-step scheme and its first step scheme achieve 99.42 and 99.23% reduction in average switching energy, respectively, and have no reset energy consumption. Moreover, 86.7 and 75% reduction in unit capacitor number over the conventional scheme are also achieved.

2 Energy analyses

For most of the switching energy is consumed in the first several bit cycles, it is a key point to reduce the switching energy of the first several bit cycles to zero, Analyze the switching energy as follows:

In every bit cycle, the bottom voltage of some capacitors is changed, while the others remain unchanged. The switching energy of these two kinds of capacitors is
$$ E_{i} = {\text{V}}_{i} {\text{C}}_{i} \left[ {\left( {{\text{V}}_{i} - V_{y} } \right) - \left( {V_{i} - {\text{V}}_{x} } \right)} \right] $$
$$ E_{j} = V_{yj} C_{j} \left[ {\left( {V_{yj} - V_{y} } \right) - \left( {V_{xj} - V_{x} } \right)} \right] $$

The subscript “i” represents the quantities of the unchanged capacitors, while “j” represents the changed capacitors. The subscript “y” represents the quantities after the switching, and “x” represents the quantities before the switching.

$$ {\text{V}}_{y} - {\text{V}}_{x} = \mathop \sum \limits_{j} \frac{{C_{j} \Delta V_{j} }}{{C_{tot} }} $$
In most instances, the voltage change quantity on the bottom plate of every Cj is the same, so:
$$ \Delta V = \Delta V_{j} $$
$$ {\text{k}} = \mathop \sum \limits_{j} \frac{{C_{j} }}{{C_{tot} }} $$
$$ E_{i} = - kV_{i} C_{i} \Delta V $$
$$ E_{j} = V_{yj} C_{j} \Delta V\left( {1 - k} \right) $$
$$ {\text{E}} = \mathop \sum \limits_{i} E_{i} + \mathop \sum \limits_{j} E_{j} $$
$$ {\text{E}} = \Delta V\left( {\mathop \sum \limits_{j} V_{yj} C_{j} (1 - k) - \mathop \sum \limits_{i} V_{i} C_{i} k} \right) $$

There are several ways to let E = 0.

2.1 The first way

If the bottom plates of all the capacitors are set to the same voltage (\( {\text{for}}\,{\text{any}}\, i,j,\;V_{i} = V_{yj} ) \):
$$ {\text{E}} = V_{i} \Delta V\left( {\mathop \sum \limits_{j} C_{j} (1 - k) - \mathop \sum \limits_{i} C_{i} k} \right) $$
$$ \mathop \sum \limits_{i} C_{i} k = \mathop \sum \limits_{i} C_{i} \mathop \sum \limits_{j} \frac{{C_{j} }}{{C_{tot} }} = \frac{1}{{C_{tot} }}\mathop \sum \limits_{i} C_{i} \mathop \sum \limits_{j} C_{j} $$
$$ \mathop \sum \limits_{j} C_{j} (1 - k) = \mathop \sum \limits_{j} C_{j} \mathop \sum \limits_{i} \frac{{C_{i} }}{{C_{tot} }} = \frac{1}{{C_{tot} }}\mathop \sum \limits_{i} C_{i} \mathop \sum \limits_{j} C_{j} = \mathop \sum \limits_{i} C_{i} k $$
Plug (11), (12) into (10):
$$ {\text{E}} = 0 $$

2.2 The second way

If the bottom plate voltage of all the capacitors are changed and changed in the same quantity (\( \sum\nolimits_{j} {C_{j} } = C_{tot} ,\,\,\sum\nolimits_{i} {C_{i} } = 0,\,\, {\text{k}} = 1) \)). It is easy to get \( {\text{E}} = 0 \).

2.3 The third way

$$ \mathop \sum \limits_{j} V_{yj} C_{j} (1 - k) = \mathop \sum \limits_{i} V_{i} C_{i} k $$

It is easy to get \( {\text{E}} = 0 \), but it is difficult to find a special voltage distribution [6].

2.4 The fourth way

In some cases, we can get a negative E, so it’s seems that the zero switching energy consumption can be achieved by \( E_{P} + E_{n} = 0 \) (\( E_{P } \) is the energy consumption of P-DAC, and \( E_{N} \) is the energy consumption of N-DAC). But, a special voltage distribution should be applied [6].

3 Proposed switching scheme

Figure 1 shows the proposed switching scheme of an 8-bit SAR ADC. The scheme adopts a two-step architecture that each step decides 4 bits.
Fig. 1

The illustration of the proposed 8-bit SAR ADC

3.1 The first step

The first part of the proposed architecture is equivalent to an independent 4-bit SAR ADC as shown in Fig. 2. The MSB capacitor 2C split into two capacitor (C, C) because of the MSB-split structure. In the end of the sampling phase, the input singles are sampled onto the top plates of the DAC, while the bottom plates of LSB sub-arrays are set to GND, and the MSB sub-arrays are set to Vcm, where Vcm equals to half of the voltage reference Vref. ‘1’, ‘1/2’ and ‘0’ represent the voltage reference Vref, Vcm and ground (GND). After sampling, we can get the MSB (D1) directly by comparing the inputs without any switching. Based on the MSB (D1), the voltage of all the bottom-plates of the lower input referred capacitor array are increased by Vcm, being changed to [Vref, Vref, Vcm, Vcm]. The other capacitor array remain unchanged. Thus, the MSB-1(D2) is obtained, and no switching energy is consumed in this operation due to “the first way”. During the third bit cycle, if D2 and D1 are not equal, the side with [Vcm, Vcm, GND, GND] is changed to [Vcm, Vcm, Vcm, Vcm], while the other side remain unchanged. If D2 is equal to D1, the side with [Vcm, Vcm, GND, GND] is changed to [GND, GND, GND, GND]. Due to “the second way”, this operation consumes zero switching energy. So far, there is no switching energy consumption in the first three bit-cycles with the proposed scheme.
Fig. 2

The first part of the proposed switching scheme for a 4-bit SAR ADC

In the following bit cycles, a single-side switching method is applied. As shown in Fig. 1, the side with [Vcm, Vcm, Vcm, Vcm] or [GND, GND, GND, GND] is always unchanged, and the other side capacitor array switch with only two reference voltages, following the scheme proposed by [3].

3.2 The second step

During the first step, after the first two switching cycles, only one of the two capacitor DACs keep working in the rest bit cycles, and the other one always remain unchanged. Based on this factor, a new scheme is proposed, as shown in Fig. 3, to reduce the number of unit capacitor. The second part capacitor array includes a 4-bit MSB-split capacitor array and a redundant capacitor Crest. During the first step, all the plates of the second part capacitor array are set to Vcm. When the first step is complete, connect the second part capacitor array with the DAC that worked in the first step, turn off S1, S2, S3 and turn on S4, as shown in Fig. 3 for example. Then, we can get the last 4 bits by the scheme proposed by [3]. The number of Crest can be get by the following equations [7].
$$ C_{tot} = C_{rest} + C_{MSB} + C_{LSB} $$
$$ \frac{1}{2}V_{ref} \frac{{C_{MSB} }}{{C_{tot} }} = \frac{1}{{2^{N/2} }}V_{ref} $$
$$ C_{MSB} = C_{LSB} $$
$$ \frac{1}{2}V_{ref} \frac{C}{{C_{tot} }} = \frac{1}{{2^{N - 1} }}V_{ref} $$
C is the unit capacitor; N is the total bit of the ADC.
Fig. 3

The second part of the proposed switching scheme

Compared with the symmetrical architecture, the proposed one only need one capacitor-based DAC in the second part, which achieves nearly 50% reduction in the unit capacitor number.

S1–S5 will affect the accuracy of the ADC in two respects.

The first respect, the switch is made up of MOSFET, so it’s inevitable to introduce stray capacitance in the DAC, and effect the upper plate voltage of the capacitor array DAC.
$$ \Delta V_{DAC1\_real} = \Delta V_{DAC1} \frac{1}{{1 + {\raise0.7ex\hbox{${\left( {C_{S5} + C_{S1} } \right)}$} \!\mathord{\left/ {\vphantom {{\left( {C_{S5} + C_{S1} } \right)} {C_{all1} }}}\right.\kern-0pt} \!\lower0.7ex\hbox{${C_{all1} }$}}}} $$
$$ \Delta V_{DAC2\_real} = \Delta V_{DAC2} \frac{1}{{1 + {\raise0.7ex\hbox{${\left( {C_{S3} + C_{S4} } \right)}$} \!\mathord{\left/ {\vphantom {{\left( {C_{S3} + C_{S4} } \right)} {C_{all2} }}}\right.\kern-0pt} \!\lower0.7ex\hbox{${C_{all2} }$}}}} $$

ΔVDAC1_real and ΔVDAC2_real are the real upper plate voltage change of the capacitor array DAC, and ΔVDAC1, ΔVDAC1 are the theoretical value. CSx is the stray capacitance of switch. Callx is the total capacitance of the capacitor array. In the second step, both plates of C1 are floating, so the effect on C1 can be ignored. Minish the array of the switching tube can decrease the stray capacitance. If necessary, a digital calibration could be introduced.

The second respect, when the switches move, the leak current will affect the DAC’s voltage. Using the transmission gate with both N-MOS and P-MOS and choosing a reasonable aspect ratio could minimize the leak current.

4 Reset energy

After the second step, the first and second part capacitor array is separated by turning off S4. It consume no energy to reset all the bottom plates of the second part capacitor array to Vcm due to “the first way”. However, it will result in a huge energy consumption if we reset the first part capacitor array to the original state in the next moment. To reduce the reset energy, we use a scheme shown in Fig. 4. Figure 4(1) shows a capacitor array of the first part, which we cannot make sure the voltage distribution on its bottom plates. Turn off S5 and all the switches between the bottom plates and the reference voltage, and short the MSB and LSB respectively [8]. Then, the MSB is changed to Vcm while the LSB is changed to Gnd. Due to “the second way”, this operation draw no energy from the reference voltage. Next, the MSB and LSB sample the input respectively. When the sampling is finished, S5 is turned on, and a new SAR cycle begins. Since both the up-plate voltage of the MSB and LSB is Vin, there is no charge redistribution in this operation, which means there is no energy consumption. From the above, the reset energy is reduced to zero theoretically.
Fig. 4

Illustration of the reset scheme

5 Simulation

The behavioural simulations for the case of 10 bit ADC were performed in MATLAB to compare the two proposed schemes with several existing ones. A comparison of average energy consumption is shown in Fig. 5 and 6 and summarized in Table 1. Without consideration of the PART 2, the average switching energy of a 10 bit SAR ADC with the switching scheme proposed in PART 1 is 10.54CV ref 2 , which achieves a 99.23% reduction over the conventional architecture. When both the two proposed parts is applied, the average switching energy is only 7.91CV ref 2 . Besides the switching energy saving, both the two proposed scheme have no reset energy while (Fig. 4(5)) consume a huge energy in resetting. In the respect of unit capacitor saving, the number of unit capacitor used in the two proposed scheme is 512 and 272 respectively, which is 4096 in the conventional architecture, achieving 75 and 86.7% reduction.
Fig. 5

Switching energy against output codes for the first scheme

Fig. 6

Switching energy against output codes for the total scheme

Table 1

Comparison of several switching schemes for 10-bit ADC

Switching scheme

Switching energy (CV ref 2 )

Switching energy saving

Reset energy (CV ref 2 )

Total energy saving

Unit capacitor saving

Conventional [2]






VCM-monotonic [9]






Vcm-based [10]






MSB-split-VCMbased [3]






Tri-level [1]






Proposed-part 1












6 Conclusion

Two energy-efficient and area-efficient switching scheme is presented in this paper. The switching energy is reduced by 99.23 and 99.42% respectively, while no reset energy is consumed. The number of unit capacitor is reduced by 75 and 86.7%. Therefore, it is applicable to use the proposed schemes in the biomedical area.



This work was supported by the National Natural Science Foundation of China (61625403, 61504104).


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Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (, which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Authors and Affiliations

  1. 1.School of MicroelectronicsXidian UniversityXi’anChina

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