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A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage

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Abstract

In this paper, we propose a comparator-based switched-capacitor (CBSC) architecture using a multi-level input tracking preset voltage scheme. The CBSC is used to compensate for technology scaling and to reduce the power consumption of a 2.8 MS/s 10-bit cyclic analog-to-digital converter (ADC). A multi-level preset voltage tracks the input voltage in order to improve the conversion rate without consuming additional power. Additionally, a comparator, current sources, and a feedback capacitor are shared to reduce the power and area of this cyclic ADC. Near the Nyquist-rate, a prototype implemented in 0.18 μm CMOS technology has a signal-to-noise and distortion ratio of 53.69 dB and a spurious-free dynamic-range of 62.36 dB, while consuming 0.73 mW of power.

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Authors and Affiliations

  1. Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA

    Jong-Kwan Woo

  2. Electrical Engineering, Seoul National University, Seoul, Korea

    Taehoon Kim & Suhwan Kim

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  1. Jong-Kwan Woo
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  2. Taehoon Kim
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Correspondence to Jong-Kwan Woo.

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Woo, JK., Kim, T. & Kim, S. A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage. Analog Integr Circ Sig Process 81, 729–739 (2014). https://doi.org/10.1007/s10470-014-0406-x

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  • DOI: https://doi.org/10.1007/s10470-014-0406-x

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