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A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology

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Abstract

A quarter-rate 4-tap decision feedback equalizer (DFE) using new analog sampling and soft-decision technique is proposed in this paper. The proposed DFE introduces two optimizations on basis of the original soft-decision DFE. Firstly, implementation of sample-and-hold circuit is changed into the cascade transmission gates to simplify the clock generation. Secondly, 4-tap structure is realized without increasing any hardware complexity to enhance the ability of equalization. To verify the DFE, a simplified transceiver is designed and fabricated in UMC 0.18-μm CMOS process, which mainly consists of a 4-tap DFE, a clock receiver and generator and a 4 to 1 multiplexer. The measurement results show that the quarter-rate 4-tap DFE can equalize 9 Gb/s 27−1 PRBS data passed over a 20 cm FR-4 channel with 16.3 dB of loss at 4.5 GHz and achieve 0.46UI timing margin for bit error rate = 10−12. The active area of the whole transceiver is 0.65 × 0.24 mm2, while the DFE occupies 0.13 × 0.18 mm2 and draws 7.2 mA from 1.8 V supply.

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Acknowledgments

This work is supported by The National High Technology Research and Development Program of China (863 Program), No. 2013AA014302.

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Authors and Affiliations

  1. Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing, 100084, China

    Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Liji Wu, Chun Zhang & Zhihua Wang

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  1. Shuai Yuan
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  2. Ziqiang Wang
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  3. Xuqiang Zheng
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  4. Liji Wu
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  5. Chun Zhang
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Correspondence to Liji Wu.

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Yuan, S., Wang, Z., Zheng, X. et al. A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology. Analog Integr Circ Sig Process 81, 777–788 (2014). https://doi.org/10.1007/s10470-014-0404-z

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