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Combination of DAC switches and SAR logics in a 720 MS/s low-bit successive approximation ADC

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Abstract

In this paper a 4-bit 720 MHz low-power successive approximation register ADC is simulated in a 0.18 µm digital CMOS process. By using both of the 2-bit/step and time-interleaved techniques, a high sampling frequency is obtained. To simplify the SAR ADC in low-bit applications, the analog switches are eliminated and replaced with inherent digital switches of SAR logics. The power supply, resolution, sampling frequency, SNDR, and power consumption of the proposed SAR ADC are 1.8 V, 4-bit, 720 MHz, 22.1 dB, and 10 mW.

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Authors and Affiliations

  1. Iran University of Science and Technology, Tehran, Iran

    Masumeh Damghanian

  2. K. N. Toosi University of Technology, Tehran, Iran

    Hossein Shamsi

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  1. Masumeh Damghanian
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  2. Hossein Shamsi
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Correspondence to Masumeh Damghanian.

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Damghanian, M., Shamsi, H. Combination of DAC switches and SAR logics in a 720 MS/s low-bit successive approximation ADC. Analog Integr Circ Sig Process 80, 263–272 (2014). https://doi.org/10.1007/s10470-014-0337-6

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  • DOI: https://doi.org/10.1007/s10470-014-0337-6

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