Abstract
A low power phase locked loop (PLL) based transmitter for wireless sensor application is presented in this paper. The transmitter adopts two-point modulation architecture in high-pass and low-pass paths of PLL; it modulates the divide ratio through sigma-delta modulator and voltage controlled oscillator (VCO) frequency tuning port simultaneously. An interleave-biased varactor pair is used to linearize the frequency tuning curve of the VCO. Besides, to achieve the desired frequency deviation of 500 kHz, we use a capacitance desensitization technique through combined parallel and serial capacitances with tuning varactors. This topology does not need the minimum size varactor, which is sensitive to process variation and mismatch. Implemented in standard 0.18-μm CMOS process, the transmitter achieves a 5.2 % FSK error for 2 Mbps data rate without using any auto-calibration circuit, consuming 7.8 mW power. Loop filter and crystal are the only off-chip components.
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Acknowledgments
This work was supported by the USTC and IMECAS jointed lab Micro-Nano electronic System Integration R&D (MESIC) under MESIC Grant No. 2100230011. The authors wish to thank Jingye Sun, Wei Hu, Chuankui Shen for circuits discussion and FPGA test code implementation. We appreciate the Information Science and Technology center of USTC for CAD support and Agilent for measurement support.
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Wang, C., Diao, S., Chen, N. et al. A calibration-less low error two-point modulation transmitter for 802.15.4 application. Analog Integr Circ Sig Process 80, 273–282 (2014). https://doi.org/10.1007/s10470-014-0329-6
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DOI: https://doi.org/10.1007/s10470-014-0329-6