1 Introduction

DC–DC converter has been regarded as the core of the power management unit. Nowadays, dynamic voltage scaling (DVS) is widely used to reduce power consumption by adjusting the supply voltage of the system. Thus it urgently needs to develop the DC–DC converter whose output voltage can be dynamically regulated with fast response speed. Apart from the high power conversion efficiency, two other considerations should be taken into account in DVS enabled converter. One is the demanding requirement in transient response [1–3], and the other is the range of the output voltage. Power supply voltage becomes lower and lower in system-on-chip (SoC) integration due to the technology shrinking tendency. Thus DC–DC converters with high dynamic response and low minimum output voltage have attracted more and more attentions.

Many techniques have been proposed to improve the transient behaviors of the switching DC–DC converters. To speed up the transient response, a dual-mode control is proposed in [4], which enables hysteretic control during transient and resumes normal voltage-mode control at steady state. In [5, 6], a fast transient recovery circuit is proposed to achieve a high slew rate of load variation in a voltage-mode Buck converter. In [7, 8], a pulse-train control scheme and a PWM controller are reported. Two states can be transited seamlessly depending on the dynamic operating status. All above techniques are aimed at the non-DVS system and they distinguishes the operating mode of the converter by a fixed threshold band. However, in the DVS utilization, different thresholds are required because the output voltage of the converter is dynamically changed. It brings some difficulties on the loop analysis and transient design.

Moreover, for a DVS enabled system, transient behaviors become more important especially on the output voltage tracking features. Actually, state trajectory is a good method to help us know more behavior details about the switching DC–DC converters. In [9], state trajectory is used to analyze the transient response of the switching converter and a free-running control law is developed. Based on the state trajectory predictions, an enhanced free-running control law is proposed in a hysteretic Buck converter to improve the transient behaviors [10]. As a result, the output voltage can reach its steady state within two switching periods even under a large transient step. State trajectory is used to study the large signal stability of the switching converter in [11].

In this paper, a DVS-enabled Buck converter with low output voltage and fast transient response is presented. State trajectory is used to analyze the transient behaviors of PWM and PFM Buck converters, respectively. A transient enhancement circuit is proposed to improve the transient and overshooting of the converter. Additionally, a current-starved voltage controlled delay line (VCDL) is designed in the controller to reduce the minimal output voltage of the converter. The proposed DVS-enabled Buck converter is designed in a 0.18 μm CMOS technology. It can dynamically regulate the voltage from 0.5 to 2.0 V with an input voltage of 3.3 V. The output-voltage and load tracking capability are both improved greatly.

The transient features of different converters are discussed by using state trajectory in Sect. 2. The structure and the detailed circuit implementation of the proposed DC–DC converter are described in Sect. 3. The design results and the chip layout are provided in Sect. 4. Finally, conclusion is given in Sect. 5.

2 Transient analysis of the converters by state trajectory method

There exist different mathematical methods to analyze the switching DC–DC converters. State trajectory is regarded as one of the good methods to examine the transient behaviors [9]. In this section, state trajectory is employed to analyze the transient response of a voltage-mode PWM Buck converter and a hysteretic PFM Buck converter, respectively.

2.1 State trajectories of the Buck converter

The schematic diagram of a Buck converter is shown in Fig. 1. Its behavior can be represented mathematically by a sequence of differential equations. Then the time-domain state solutions can be obtained. For different time intervals, the corresponding state equations are as follows:

Fig. 1
figure 1

Schematic diagram of the Buck converter

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When M1 is on and M2 is off, the time-domain differential equations are

$$\left\{ {\begin{array}{*{20}l} {L\frac{{di_{L} }}{dt} = V_{in} - \left( {v_{C} + C\frac{{dv_{C} }}{dt} \times R_{C} } \right) - R_{L} \times i_{L} } \hfill \\ {C\frac{{dv_{C} }}{dt} = i_{L} - \frac{1}{{R_{load} }} \times \left( {v_{C} + C\frac{{dv_{C} }}{dt} \times R_{C} } \right)} \hfill \\ \end{array} } \right.$$
(1)

The inductor current i L and the capacitor voltage v C are state variables. V in is the input voltage of the Buck converter, R load is the load resistance. R C and R L are the parasitic resistance of the capacitor and the inductor, respectively. v C(t 0) and i L(t 0) represent the arbitrary initial state variables of the converter, and t 0 is an arbitrary initial time.

Similarly, when M1 turns off and M2 turns on, the differential equations are

$$\left\{ {\begin{array}{*{20}l} {L\frac{{di_{L} }}{dt} = - \left( {v_{C} + C\frac{{dv_{C} }}{dt} \times R_{C} } \right) - R_{L} \times i_{L} } \hfill \\ {C\frac{{dv_{C} }}{dt} = i_{L} - \frac{1}{{R_{load} }} \times \left( {v_{C} + C\frac{{dv_{C} }}{dt} \times R_{C} } \right)} \hfill \\ \end{array} } \right.$$
(2)

These differential equations, when plotted in a state plane of i L versus v C, are defined as the state trajectories. In Fig. 2, the directional dash lines are called M1-on trajectories which decided by Eq. (1). The directional solid lines are M1-off trajectories which decided by Eq. (2). The operations of the converter can be observed as series trajectory connections of M1-on and M1-off. The closed curve, which consisting of one M1-on trajectory and one M1-off trajectory, is one steady-state of the converter.

Fig. 2
figure 2

Families of M1-on trajectories (directional dash lines) and M1-off trajectories (directional solid lines) in the state plane of i L versus v C with V in = 3.3 V, L = 5 μH, C = 1 μF and R load = 4 Ω. Directional closed curve ABA represents one of the steady-state trajectories

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2.2 Transient response comparison based on state trajectory

To show the transient behaviors, a voltage-mode PWM Buck converter and a hysteretic PFM Buck converter are built, where V in is 3.3 V, the filter capacitor C is 1 μF, the inductor L is 10 μH, the output load R load is 4 Ω and the parasitic resistance of inductor and capacitor are all 50 mΩ. The switching frequency f s is 800 kHz. When the above parameters are substituted in Eqs. (1) and (2), the state trajectories corresponding to an output-voltage step changed from 1.08 to 2.2 V and a load-current step changed from 412.5 to 206.25 mA for the voltage-mode PWM Buck converter are shown in Fig. 3(a, b), respectively, where “A” represents the initial state and “B” is the final state. The state of the converter alternately follows M1-on and M1-off trajectories in the state plane, and eventually, converges to a closed steady-state trajectory curve. Two adjacent segments of state trajectories represent an on/off switching cycle. The state trajectories of the hysteretic PFM Buck converter with an output-voltage step change from 1.08 to 2.2 V and a load-current step change from 412.5 to 206.25 mA are also shown in Fig. 3(c, d), respectively.

Fig. 3
figure 3

State trajectories of Buck converters: a PWM converter with output-voltage step change, b PWM converter with load-current step change, c PFM converter with output-voltage step change and d PFM converter with load-current step change

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Comparing the transient response behaviors in Fig. 3, we can see that the hysteretic PFM converter exhibits faster transient features than the voltage-mode PWM converter either in the output-voltage step change or the load-current step change because fewer switching cycles are needed to reach the final steady state. For the DVS applications, in order to speed up the transient behaviors the hysteretic control is selected in this work.

3 System design and circuit implementation of the proposed converter

3.1 DVS operation and system topology

A DVS system block diagram is shown in Fig. 4 [12]. It consists of a DVS-enabled DC–DC converter, a microprocessor and a DVS algorithm block. The DVS-enabled DC–DC converter provides the dynamically regulated voltage V DD to the microprocessor. The software algorithm is employed in the microprocessor to calculate the optimal supply voltage for maintaining the minimum power dissipation of the microprocessor. The power stage block, hysteretic controller and VCDL constitute a basic DVS-enabled DC–DC converter. Frequency signal f ref is sent to the VCDL. By detecting the phase difference between f ref and the output signal f delay of the VCDL, the hysteretic controller generates different duty ratio signals to control the on/off of the power transistors providing the required optimal supply to the microprocessor. In addition, sometimes, in order to improve the voltage tracking capability, the transient enhancement circuit is added for DVS system. Note that the output voltage of converter V DD is also the control voltage V ctrl of VCDL, which determines the time delay of the VCDL.

Fig. 4
figure 4

Block diagram of a DVS system with hysteretic Buck converter

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3.2 Design of the transient enhancement circuit

For DVS application, switching DC–DC converters should have fast voltage tracking speed. Many techniques have been proposed to improve the transient behaviors. In [13], a fast transient double Buck converter is proposed. Two control mode are used to achieve linear and nonlinear control strategies during the steady and transient period, respectively. It speeds up the transient speed greatly. In this paper, we give the state trajectory analysis of the double Buck converter and then proposed a novel transient enhanced double Buck converter.

3.2.1 Transient response of the previous double Buck technique

Figure 5 shows a voltage-mode double Buck converter architecture [13]. A main converter and an auxiliary converter are connected in parallel. They play different roles in the converter. The main converter focuses on the loop stability and the low output voltage ripple, while the auxiliary converter provides or takes out current from the output when the output voltage exceeds the voltage thresholds.

Fig. 5
figure 5

Block diagram of the double Buck converter

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We can also apply the hysteretic control in the double Buck converter. The corresponding parameters are: V in = 3.3 V, the inductance of main inductor L 1 is 10 μH, the auxiliary inductance L 2 = 2 μH, the filter capacitance C = 1 μF and R load is 4 Ω. The parasitic resistance of L 1, L 2 and C are all 50 mΩ. The threshold band of hysteretic control is defined as 0.1 V. The state trajectories are therefore obtained, shown in Fig. 6.

Fig. 6
figure 6

State trajectories of the double Buck converter during transient periods: a output-voltage step change and b load-current step change

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Figure 6(a) illustrates the state trajectories for an output-voltage step from 1.08 to 2.2 V. After several switching periods, the converter state moves from the initial steady state “A” into the threshold band and gradually arrives at the final steady state “B”. For double Buck, if the output voltage is within the threshold band, only the main switching converter operates. It likes a typical Buck converter. If the output voltage goes out of the threshold band, the auxiliary converter works. In Fig. 6(a), when the state trajectory enters the threshold band, the auxiliary converter should stop operating. However, because a large quantity of current have stored in L2 during the up-step transient, the current continues to charge the filter capacitor through the parasitic diode D1 of Mn2. It forces the state trajectory run out of the threshold band again. In order to make the output voltage go back into the threshold band, Mn2 should be turned on to discharge the filter capacitor C. But the discharging behavior could not take effect until the current stored in L2 exhausts and begins to reverse. As a result, an unexpected inductor current oscillation occurs, which resulting the state trajectory path of NOPQ, slows down the voltage tracking speed of the converter.

During the transient period of a load-current change of 412.5–206.25 mA, as shown in Fig. 6(b), the current stored in L2 is not large enough to generate the oscillation explained above. Thus a relatively faster recovering time and lower overshooting voltage are obtained.

Compared to the state trajectories of the single Buck converter shown in Fig. 3(c, d), the double Buck converter has less voltage overshooting and exhibits better transient behaviors.

3.2.2 New transient enhanced double Buck converter

Previous double Buck converter suffers from the inductor current oscillation. Moreover, when there is a large output-voltage variation, such as the converter start-up period, it suffers from large voltage overshooting. To solve this problem, a novel transient enhancement circuit is proposed in this work.

The structure of transient enhancement circuit is shown in Fig. 7. It is composed of a main power converter loop and two auxiliary current paths. Mn2 and L2 constitute one auxiliary path while Mp2 and L3 constitute the other one. D2 and D3 are two current bypasses. Two current bypasses degrade the inductor’s current in terms of the RL loop. Because they are totally independent of the main converter loop, it will not induce the non-stability issues.

Fig. 7
figure 7

New transient enhanced double Buck converter

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Table 1 lists the operation mode of the proposed converter, where V o is the output voltage and 2ΔV o represents the threshold band. For the DVS application, V o is dynamically changed. If the output voltage is within the threshold range, only the main converter loop works. Difference appears when the state trajectory moves into the threshold band. For the pervious double Buck converter, the auxiliary converter is forced to shut down, the current stored in L2 is charged or discharged through the parasitic diodes of Mp2 or Mn2. Since the charge and discharge actions have to be completed through one current path and the direction of the auxiliary inductor current could not be changed instantaneously, it needs longer transient recovery time. However, for the proposed structure, although the power switches are disabled during the transient period, the current bypass diode D2 and D3 provide the auxiliary current path to avoid the same charge and discharge path described above.

Table 1 Operation mode of the proposed converter
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The state trajectories are drawn to illustrate the transient response of the converter. L2 and L3 are both 2 μH and the threshold band 2ΔV o is 0.1 V. The state trajectories of the converter with an output-voltage step change and a load-current step change are presented in Fig. 8. As shown in Fig. 8(a), after passing point “M”, the state trajectory staggers along the low threshold boundary and moves into the threshold band. Consequently, oscillation appears in Fig. 6(a) is avoided. The load transient behavior in Fig. 8(b) is similar with that of Fig. 6(b). The proposed transient enhancement circuit maintains excellent current-step transient characteristic and exhibits superior voltage-step transient characteristics, which shows more attractive for the DVS applications.

Fig. 8
figure 8

State trajectories of the proposed converter in transient periods: a output-voltage step change and b load-current step change

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3.3 Current-starved VCDL for lowering the minimum output voltage of the converter

3.3.1 Operational principle of VCDL based Buck converter

VCDL is used to construct a hysteretic controller, as shown in Fig. 9(a). It consists of quantities of delay cells. When a frequency signal of f ref is applied to the input of VCDL, it passes through delay cells and being sampled by f ref again at the output. The propagation delay t delay is determined by the control voltage V ctrl, which is equals to the output voltage of converter. When V ctrl decreases, t delay increases. The falling edge of the delay signal passes the sampling edge, as shown in Fig. 9(b). The output of D flip–flop becomes “1” and power transistor Mp turns on. The inductor is charged and the output voltage increases. On the contrary, if V ctrl increases, t delay decreases. The falling edge of delay signal does not reach the sampling edge, as shown in Fig. 9(c). The output of D flip–flop keeps its initial value of “0”. In this case, the inductor is discharged and the output voltage of the converter is reduced. On the other hand, if f ref decreases, the falling edge of the delay signal will not reach the sampling edge, as shown in Fig. 9(d). The output of D flip–flop becomes “0”, and the inductor discharges current from output capacitor, resulting decrease of the output voltage. Similarly, for a increased f ref, as shown in Fig. 9(e), the output voltage is increased.

Fig. 9
figure 9

Operational principle of VCDL based Buck converter: a block diagram of the VCDL based Buck converter and the waveforms when b V out decreases, c V out increases, d f ref decreases and e f ref increases

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When the VCDL based Buck converter is operating in its steady state, the propagation delay t delay and f ref satisfy the following relationship:

$$t_{delay} = \frac{1}{{2f_{ref} }}$$
(3)

For the DVS-enabled converter, an excellent linearity between the output voltage and the reference frequency f ref is required. An inverse proportion between the control voltage V ctrl and the delay time t delay is required to compensate the nonlinearity between t delay and f ref according to Eq. (3).

3.3.2 Current-starved VCDL

In order to regulate the output voltage as low as 0.5 V, VCDL should effectively operate in sub-threshold region. Traditional CMOS-inverter based VCDL shows approximate inverse-proportion feature between V ctrl and t delay when V ctrl is much higher than the threshold voltage of the MOSFETs. But when V ctrl is lower or approximate to the threshold voltage, CMOS-inverter based VCDL lost the good inverse-proportion feature between V ctrl and t delay. In this work, a current-starved VCDL is proposed to improve the non-linearity at low voltage under the threshold voltage of the MOSFETs. The current-starved VCDL is shown in Fig. 10, which consists of quantities of current-starved inverters and a V–I converter. By controlling the charge or discharge current of the output parasitic capacitor of each current-starved inverter, the propagation delay of the delay line can be regulated. Time delay of one current-starved inverter is as follows [14]:

$$t_{delay\_inv} = \frac{{C_{tot} \times V_{dd} }}{{I_{D} }}$$
(4)

where C tot is the equivalent parasitic capacitance of the inverter. It is a constant. V dd is the power supply voltage of VCDL and I D is the bias current of the inverter.

Fig. 10
figure 10

Schematic of the proposed current-starved VCDL

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A V–I converter is designed to achieve a linear variation of t delay_inv. The structure of V–I converter is shown in Fig. 10. Mp1 is controlled by V ctrl. The symmetrical bias voltages V bp and V bn provide DC operating conditions of the transistors. They also determine the charging or discharging current I D of C tot. Mn1, Mn2 and Mn4 have the same dimensions, while Mp2 and Mp3 have the same dimensions. Mp1 operates in the linear-region. A bias voltage of V bias, which is a little higher than V dd, is added to the bulk of Mp2 to lower the threshold voltage of Mp2. Following equations can be obtained:

$$\left\{ {\begin{array}{*{20}l} {(V_{GS} )_{Mp2} = (V_{GS} )_{Mp3} + (V_{DS} )_{Mp1} } \hfill \\ {(V_{TH} )_{Mp2} = V_{THp0} + \gamma (\sqrt {\left| {2\phi_{F} + V_{dd} - V_{bias} } \right|} - \sqrt {\left| {2\phi_{F} } \right|} )} \hfill \\ {(V_{DS} )_{Mp1} \approx - \frac{{(I_{drain} )_{Mp1} }}{{(k)_{Mp1} [V_{ctrl} - V_{dd} - (V_{TH} )_{Mp1} ]}}} \hfill \\ \end{array} } \right.$$
(5)

where V GS is the gate voltage, V DS is the voltage between drain and source, V TH is the threshold voltage and ϕ F is the Fermi potential. That is,

$$- \sqrt {\frac{{2\left| {(I_{drain} )_{Mp2} } \right|}}{{(k)_{Mp2} }}} + (V_{TH} )_{Mp2} = - \sqrt {\frac{{2\left| {(I_{drain} )_{Mp3} } \right|}}{{(k)_{Mp3} }}} + (V_{TH} )_{Mp3} - \frac{{(I_{drain} )_{Mp1} }}{{(k)_{Mp1} [V_{ctrl} - V_{dd} - (V_{TH} )_{Mp1} ]}}$$
(6)

where I drain is the drain current of the MOSFET and k is the transconductance coefficient. Considering that,

$$(I_{drain} )_{Mp1} = (I_{drain} )_{Mp2} = (I_{drain} )_{Mp3} = - I_{D}$$
(7)
$$(V_{TH} )_{Mp2} = (V_{TH} )_{Mp3} = V_{THp0}$$
(8)
$$(k)_{Mp1} = (k)_{Mp2} = (k)_{Mp3}$$
(9)

From equations from (6) to (9), we can obtain

$$I_{D} = K \times (V_{ctrl} - V_{dd} - V_{THp0} )$$
(10)

where \(K = \gamma \times (\sqrt {\left| {2\phi_{F} + V_{dd} - V_{bias} } \right|} - \sqrt {\left| {2\phi_{F} } \right|} ) \times (k)_{Mp1}\). V THp0 and K are both process-related constants. γ is the substrate bias coefficient, γ < 0.

Assuming there are N stage current-starved inverters in the VCDL, the total delay t delay of the VCDL is obtained by combining Eqs. (4) and (10).

$$t_{delay} = \frac{{N \times C_{tot} \times V_{dd} }}{{K \times (V_{ctrl} - V_{dd} - V_{THp0} )}}$$
(11)

Therefore, combining Eqs. (3) and (11), the linear relationship between V ctrl and f ref is obtained as follows:

$$f_{ref} = \frac{{K \times (V_{ctrl} - V_{dd} - V_{THp0} )}}{{2N \times C_{tot} \times V_{dd} }}$$
(12)

The current-starved VCDL can work at an ultra low voltage, even the voltage a little higher than 0 V is acceptable, which makes it possible for the converter to regulate the ultra low output voltage of 0.5 V.

4 Circuit design and result discussion

A DVS-enabled fast transient double Buck converter with a current-starved VCDL is designed in a 0.18 μm CMOS process. The circuit configuration is shown in Fig. 11. The Clock Generator generates the periodic pulses for the Boost Circuit and the enable signals for the converter. A bias voltage V bias being a little higher than the supply voltage V in is generated by the Boost Circuit module to provide a N-well bias of the VCDL. The Control Block generates the duty variation PFM control signals, which are sent to the Dead Time and Driving Block to drive the power switches. The converter operates in three modes: the high-voltage transient mode when V out is higher than V o + ΔV, the low-voltage transient mode when V out is lower than V o − ΔV, and the steady-state mode when V out is between V o-ΔV and V o + ΔV. The voltage and current references are generated by Bandgap and the Protection Circuit provides the protections of the chip.

Fig. 11
figure 11

Topology of the proposed DVS-enabled Buck converter

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The chip layout is shown in Fig. 12. The die area is 1.75 mm × 1.33 mm, including pads and ESD protections. The post-layout simulation results of the converter with Process, Voltage and Temperature (PVT) variations are shown in Fig. 13. The same parameters as those of the hysteretic converter are used. Three process corners are simulated and the waveforms are divided into three groups, which depict the converter’s transient characteristics. Figure 13(a–d) are the results under Typical NMOS and Typical PMOS (TNTP) corner, Fig. 13(e–h) are the results under Slow NMOS and Slow PMOS (SNSP) corner and Fig. 13(i–l) are the results under Fast NMOS and Fast PMOS (FNFP) corner. Take the TNTP corner as an example, Fig. 13(a) shows the waveforms of the converter with the output voltage step between 0.5 V and 1.8 V. When the reference frequency f ref is 106 MHz, the output voltage of the converter V out is 0.5 V. When the corresponding f ref changes to 57 MHz, V out is 1.8 V. The voltage up-tracking speed of 4.74 μs/V and the down-tracking speed of 7.46 μs/V are obtained. Figure 13(b) shows the results when the output-voltage changes between 1.0 V and 2.0 V. When f ref is 92 MHz, V out is 1.0 V, while when f ref is 48 MHz, V out is 2.0 V. The voltage up-tracking speed is 2.0 μs/V and the down-tracking speed is 5.4 μs/V. Figure 13(c, d) show the waveforms when the load-current of the converter changes between 200 mA and 600 mA. When the output voltage is 0.5 V, the load up-tracking speed of 9.13 μs/A and the down-tracking speed of 33.0 μs/A are obtained. When the output voltage is 2.0 V, the up-tracking speed is 16.1 μs/A and the down-tracking speed is 15.25 μs/A. Similarly, the voltage tracking speed and the load tracking speed under SNSP corner and FNFP corner can be obtained, respectively, which are summarized in Table 2. This converter exhibits a slower transient response under the conditions of high junction temperature with SNSP corner than it does under the conditions of low junction temperature with FNFP corner. However, it is still a robust design against PVT variations.

Fig. 12
figure 12

Layout of the proposed converter

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Fig. 13
figure 13figure 13

Post-simulated waveforms with output-voltage/load-current step changes: a–d, e–h and i–l are the results under the TNTP corner, the SNSP corner and the FNFP corner, respectively. a, e, i are the results when output voltage is step-changed between 0.5 and 1.8 V. b, f, j are the results when output voltage is step-changed between 1.0 and 2.0 V. c, g, k are the results when V out = 0.5 V and output current is step-changed between 200 and 600 mA. d, h, l are the results when V out = 2.0 V and output current is step-changed between 200 and 600 mA

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Table 2 Transient response of the proposed converter with PVT variations
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Table 3 summarizes the features of the proposed converter. The output-voltage and the load-current tracking speeds are compared with those of the previous works in Tables 4 and 5, respectively. This work shows the lowest minimal output voltage and thus a wider output-voltage range. Moreover, it has a faster output-voltage tracking speed comparing with the other DVS-enabled converters. Besides this, our work shows a superior load tracking capability.

Table 3 Key features of the proposed converter
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Table 4 Comparisons of the output-voltage tracking speed
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Table 5 Comparisons of the load-current tracking speed
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5 Conclusion

A fast transient DVS-enabled Buck converter has been designed in this paper. The transient features of the voltage-mode PWM and hysteretic PFM converters are analyzed by using state trajectory. It can be concluded that PFM control shows better load and output voltage tracking capabilities than PWM control. Thus the hysteretic control is used and it also ensure the unconditional stability of the converter. Furthermore, a novel transient enhancement circuit is proposed based on the state trajectory analysis to effectively reduce the voltage oscillation and the overshooting during the mode transition. The transient recovery time of the Buck converter is improved. In hysteretic controller, the current-starved VCDL is designed to enable the output voltage of the converter reaching to a very low value of 0.5 V, which is very suitable for the low supply-voltage applications. The converter is designed in a 0.18 μm CMOS technology. Post-layout simulation results show that the converter’s output voltage can be dynamically regulated from 0.5 to 2.0 V with a load current range from 200 to 600 mA. The tracking speed is less than 7.5 μs/V for the output-voltage step from 1.8 to 0.5 V. For a load-current step from 0.6 to 0.2 A, the tracking speed is within 33 μs/A. The results show a better dynamic features compared with the other designs.